Phiroze N. Parakh

Congestion driven quadratic placement

This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe heuristics on region-based routing graphs to compute routing cost. The interplay between routing analysis and quadratic placement using growth matrix permits global treatment of congestion. Further reduction in congestion is obtained by the relaxation of pin constraints. Experiments show improvements in wireability.

Benchmarking for large-scale placement and beyond

Over the last five years, the large scale integrated circuit placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by a nontrivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper, we review motivations for benchmarking, especially for commercial electronic design automation, analyze available benchmarks, and point out major pitfalls in benchmarking. Our empirical data offers perhaps the first comprehensive evaluation of several leading large-scale placers on multiple benchmark families. We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.

CAD tools for area-distributed I/O pad packaging

The use of area interconnect packaging in high frequency microprocessors is motivated by its high-bandwidth and good power distribution capability. An MCM packaging scheme based on area-distributed I/O pads serves as the foundation of the PUMA project at the University of Michigan. Area interconnect facilitates high I/O counts, shorter interconnect routes, smaller power rails, and better thermal conductivity, all of which are important in high clock-rate digital systems. This paper introduces recently developed CAD tools that aid in the design of flip-chip area-interconnected integrated circuits. The tools permit the designer to place and route area bond pads as dictated by the layout of the microprocessor. System level issues, such as adequate power distribution and placement of area pad buffers, are addressed. The CAD system includes area pad power analysis, floorplanning, and routing tools.

Overview of complementary GaAs technology for high-speed VLSI circuits

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 /spl mu/W/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor.

Crosstalk constrained global route embedding

Route Embedding, a new method for mitigating the impact of crosstalk, is presented. It modifies a set of global-route structures to prevent timing and noise-margin violations caused by crosstalk, while maintaining routing constraints. An accurate and computationally-efficient empirical model for crosstalk impact is presented which by capturing noise and delay-changes on coupled conductors, permits a performance-driven approach to addressing crosstalk. Linearized crosstalk constraints are derived and satisfied for the expected noise and wire-delays at critical signal sinks. Unsatisfied constraints are resolved by inserting ground shields and by selective re-route through uncongested regions. Routing capacity constraints are enforced to guarantee a detailed routing solution.

Complementary GaAs technology for a GHz microprocessor

A DARPA-funded project at the University of Michigan has as a goal the development of technologies and tools needed to implement microprocessors that can be clocked at GHz speeds. A Complementary GaAs HIGFET technology from the Motorola CS-1 facility (CGaAs) is the target semiconductor process. While this technology is immature, it is years ahead of CMOS in terms of fast gate delay at low power supply voltages. A major focus of this work is advanced packaging, which supports partitioning of the design into multiple integrated circuits, each having an integration level that should be achievable in CGaAs. This paper touches on the major aspects of the project, process technology, circuit design, packaging, architecture, CAD tools and software, with an emphasis on application of the CGaAs technology.

CGaAs PowerPC FXU

The development of a PowerPC™ fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorolas 0.5—µm Complementary Gallium Arsenide process, the device operates from 0.9 to 1.9 V with a nominal frequency of 25 MHz at 1.3 V, dissipating 274 mW.