Phyllis Shi Ya Lim

Selenium Segregation for Effective Schottky Barrier Height Reduction in NiGe/n–Ge Contacts

In this letter, we report the demonstration of an effective electron Schottky barrier height (Φ_Bⁿ) reduction technology for NiGe/n-type Germanium (n-Ge) contacts using ion implantation of selenium (Se) followed by its segregation at NiGe/n-Ge interface. Se was found to segregate at NiGe/n-Ge interface after germanide formation. Nickel monogermanide was formed using a 350°C 30-s anneal. Se segregation gives Φ_Bⁿ as low as ~0.13 eV.

High-Performance Germanium

We report high-performance p-channel Ω-gate germanium (Ge) p-channel multigate field-effect transistor (MuGFET) with low-temperature Si₂H₆ surface passivation and Schottky-barrier nickel germanide (NiGe) metallic source/drain, fabricated on high-quality germanium-on-insulator (GeOI) substrates using sub-400°C process modules. As compared with other reported p-channel multigate Ge devices formed by top-down approaches, the Ge MuGFETs in this letter have a record-high ON-state current I_ON of ~450 μA/μm at V_GS - V_TH = -1 V and V_DS = - 1 V. High peak intrinsic saturation transconductance of ~740 μS/μm and low OFF-state current are reported. We also study the effect of fin or channel doping on Ge MuGFET performance. The simple MuGFET process developed using GeOI substrate would be a good reference for future 3-D Ge device fabrication.

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The demonstration of a salicidelike self-aligned contact technology for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is reported. A thin and continuous crystalline germanium-silicon (GeSi) layer was selectively formed on n+ doped gallium arsenide (GaAs) regions by epitaxy. A new self-aligned nickel germanosilicide (NiGeSi) Ohmic contact with good morphology was achieved using a two-step annealing process with precise conversion of the GeSi layer into NiGeSi. NiGeSi contact with the contact resistivity (ρc) of 1.57 Ω mm and sheet resistance (Rsh) of 2.8 Ω/◻ was achieved. The NiGeSi-based self-aligned contact technology is promising for future integration in high performance III-V MOSFETs.

-Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack

An anomalously high density of positive trapped charges was observed in thin (4.3-nm thickness) nitrided gate oxides subjected to high-field impulse stressing. Additionally, the transient stress-induced leakage current (AC-SILC) was found to be larger than the steady-state SILC (DC-SILC) in these impulse-stressed thin oxides, contrary to observations in dc-stressed thin oxides. The large AC-SILC was found to be related to the high density of positive trapped holes in the oxide. The hot-hole generation occurs via a regenerative feedback mechanism, with minimal charge relaxation due to the short duration of the impulse stress. This gives rise to an extremely high density of oxide trapped holes that were not observed under dc stress conditions. The trapped holes can be easily annealed electrically at room temperature and the annihilation of the positive oxide trapped charges is accompanied by a reduction in the AC-SILC and a higher number of interface states being created. The trapped holes can either be uni...

Self-aligned contact metallization technology for III-V metal-oxide-semiconductor field effect transistors

We report the first demonstration of III–V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to form NiGeSi, and unreacted metal was removed. A second anneal diffuses Ge and Si into GaAs to form heavily n+ doped regions, and a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. MOSFETs with the new self-aligned metallization process were realized.

Hole injection with limited charge relaxation, lateral nonuniform hole trapping, and transient stress-induced leakage current in impulse-stressed thin (<5 nm) nitrided oxides

The effective electron Schottky barrier height (ΦBN) of nickel silicide (NiSi:C) formed on silicon-carbon (Si1−yCy or Si:C) films with different substitutional carbon concentrations Csub was investigated. ΦBN was observed to decrease substantially with an increase in Csub. When Csub is increased from 0% to 1.5%, ΦBN is reduced by 200 meV. The results of this work could be useful for the reduction in contact resistance between nickel silicide and silicon-carbon source and drain in strained n-channel metal-oxide-semiconductor field-effect transistors.

III–V MOSFETs with a new self-aligned contact

This article presents a detailed investigation on the stress-induced leakage current (SILC) conduction mechanism via conduction-band electron (CBE) and valence-band electron (VBE) tunneling in thin oxides. An improved SILC model that is able to reproduce the experimental SILC over a wide range of oxide fields, and yet give a realistic level of extracted neutral trap concentration, is proposed. Calculations performed with the improved SILC model suggest that SILC conduction via neutral traps is accompanied by energy relaxation (i.e., an inelastic mechanism), irrespective of the origin (i.e., whether CBE or VBE) of the tunneling species. For both CBE and VBE tunneling, inelastic tunneling with energy relaxation (Erelax) of 1.5 and 0.8 eV, was found to fit the experimental measurements well. These values of Erelax agree with those reported in the literature.

Effect of substitutional carbon concentration on Schottky-barrier height of nickel silicide formed on epitaxial silicon-carbon films

III-V materials have significantly higher electron mobility than existing strained Si and are attractive channel material candidates for application in sub-20 nm logic technologies [1]. Good contacts to the source and drain regions of III-V channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are needed to take full advantage of III-V materials [2]. Currently, the lift-off process is widely employed to form contacts on III-V MOSFETs [3]. Selective growth of source/drain (S/D) materials with low sheet resistance has also been demonstrated for series resistance Rseries reduction [4]-[5]. To reduce Rseries further, self-aligned contacts are ultimately needed for device integration.

Improved model for the stress-induced leakage current in thin silicon dioxide based on conduction-band electron and valence-band electron tunneling

We report the first demonstration of a novel Ge2Sb2Te5 (GST) liner stressor which can be shrunk or contracted (in volume) during phase-change to realize performance enhancement in p-channel FinFETs. FinFETs with ultra-scaled gate length down to ∼4.5 nm were used. Amorphous GST (α-GST) liner has intrinsic stress that increases the p-FinFET drive current as compared to unstrained control devices. Further, when the a-GST changes phase to crystalline GST (c-GST), the GST liner contracts, leading to very high channel stress and drive current enhancement.

Self-Aligned NiGeSi Contacts on Gallium Arsenide for III-V MOSFETs

We report a novel metal stanogermanide contact metallization process for high-mobility germanium-tin (Ge_0.947Sn_0.053 or GeSn) channel p-MOSFETs. Nickel-Platinum (NiPt) alloy was used to react with GeSn to form a multi-phase Ni and Pt stanogermanide [NiGeSn+Pt_x(GeSn)_y] contact on epitaxial Ge_0.947Sn_0.053. Rapid thermal annealing of co-sputtered Ni and Pt on GeSn/Ge (100) at temperatures from 350 °C to 550 °C in N₂ was used for the stanogermanide formation. Compared with nickel stanogermanide (NiGeSn) contact, the Pt-incorporated contact, i.e. NiGeSn+Pt_x(GeSn)_y, exhibits enhanced thermal stability in a wide range of formation temperatures.