Huaxin Guo

Photoelectron spectroscopy study of band alignment at interface between Ni-InGaAs and In0.53Ga0.47As

The work function of Ni-InGaAs and the band alignment between Ni-InGaAs and In0.53Ga0.47As were investigated using photoelectron spectroscopy. The vacuum work function of Ni-InGaAs is obtained to be ∼5.1 eV using ultraviolet photoelectron spectroscopy (UPS). In addition, it was observed that the Fermi level of Ni-InGaAs is aligned to near conduction band of In0.53Ga0.47As at interface. For Ni-InGaAs formed on p-type In0.53Ga0.47As, this gives a Schottky contact with a hole barrier height of 0.8 ± 0.1 eV. Ni-InGaAs would form an ohmic contact on n-type In0.53Ga0.47As.

Self-aligned contact metallization technology for III-V metal-oxide-semiconductor field effect transistors

The demonstration of a salicidelike self-aligned contact technology for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is reported. A thin and continuous crystalline germanium-silicon (GeSi) layer was selectively formed on n+ doped gallium arsenide (GaAs) regions by epitaxy. A new self-aligned nickel germanosilicide (NiGeSi) Ohmic contact with good morphology was achieved using a two-step annealing process with precise conversion of the GeSi layer into NiGeSi. NiGeSi contact with the contact resistivity (ρc) of 1.57 Ω mm and sheet resistance (Rsh) of 2.8 Ω/◻ was achieved. The NiGeSi-based self-aligned contact technology is promising for future integration in high performance III-V MOSFETs.

III–V MOSFETs with a new self-aligned contact

We report the first demonstration of III–V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to form NiGeSi, and unreacted metal was removed. A second anneal diffuses Ge and Si into GaAs to form heavily n+ doped regions, and a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. MOSFETs with the new self-aligned metallization process were realized.

In 0.7 Ga 0.3 As channel n-MOSFETs with a novel self-aligned Ni-InGaAs contact formed using a salicide-like metallization process

Spacer-less In0.7Ga0.3As n-MOSFETs with self-aligned Ni-InGaAs contacts formed using a direct reaction between Ni and InGaAs were demonstrated. A novel salicide-like metallization process was developed to achieve self-aligned Ni-InGaAs contacts, comprising the steps of Ni reaction with InxGa1−xAs and selective removal of excess Ni. Dopantless n-MOSFETs with metallic Ni-InGaAs source/drain (S/D) and n-MOSFETs with Si-doped S/D and Ni-InGaAs contacts were compared. Si implant performed before the metallization effectively suppressed the off-state current IOFF by more than 10 times.

Self-Aligned NiGeSi Contacts on Gallium Arsenide for III-V MOSFETs

III-V materials have significantly higher electron mobility than existing strained Si and are attractive channel material candidates for application in sub-20 nm logic technologies [1]. Good contacts to the source and drain regions of III-V channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are needed to take full advantage of III-V materials [2]. Currently, the lift-off process is widely employed to form contacts on III-V MOSFETs [3]. Selective growth of source/drain (S/D) materials with low sheet resistance has also been demonstrated for series resistance Rseries reduction [4]-[5]. To reduce Rseries further, self-aligned contacts are ultimately needed for device integration.

A new self-aligned contact technology for III-V MOSFETs

We report the first demonstration of a self-aligned contact technology for III-V MOSFETs. A novel epitaxy process with insitu surface treatment was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. By precisely and fully converting the GeSi layer into NiGeSi, while diffusing Ge and Si into GaAs to form heavily n+ doped regions, a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. This is expected to significantly enhance the performance of III-V MOSFETs.

Performance boost for In 0.53 Ga 0.47 As channel N-MOSFET using silicon nitride liner stressor with high tensile stress

We report the first demonstration of a strained In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFET incorporated with a silicon nitride (SiN) liner stressor. High intrinsic tensile stress of 1.5 GPa in a 50 nm thick SiN was used for introducing lateral tensile strain in the In<inf>0.53</inf>Ga<inf>0.47</inf>As channel. SiN liner stressor was shown to provide significant drive current enhancement for the first time. In addition, an advanced gate dielectric technology (with SiH<inf>4</inf> + NH<inf>3</inf> treatment) was used for achieving low interface state densities for HfAlO gate dielectric formed on In<inf>0.53</inf>Ga<inf>0.47</inf>As. Strained In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFETs with good device performance are reported.

Germanium/Ni-InGaAs Solid-State Reaction for Contact Resistance Reduction on n + In 0.53 Ga 0.47 As

We report the first demonstration of solid state reaction between Ge and Ni-InGaAs to form mono nickel germanide contact on n In0.53Ga0.47As. This reaction was performed by isochronous annealing of Ge on Ni-InGaAs at temperatures ranging from 400 to 600 ̊C in N2 ambient. Detailed materials study on the reaction mechanism is described here. Compared with Ni-InGaAs contact, more than 60% reduction in contact resistance on n-In0.53Ga0.47As was achieved using this new contact formation scheme. INTRODUCTION High mobility III-V compound semiconductors are attractive candidates to replace strained Si channel for future high performance logic applications [1]-[4]. To realize the full potential of III-V MOSFETs, S/D engineering to achieve low series resistance RSD is required. A self-aligned metallization analogous to the salicide process in Si CMOS technology is desired for deeply scaled III-V MOSFETs. In this regard, Ni-InGaAs compound has been reported as a promising self-aligned contact for InGaAs MOSFETs [5]-[7]. However, these contacts suffer from high contact resistance RC which severely degrades device performance at small gate length. Therefore, RC needs to be reduced. In this paper, we report the demonstration of significant RC reduction for Ni-InGaAs contact through the solid state reaction of Ge and Ni-InGaAs. This was achieved by annealing the material stacks and mono nickel germanide is formed on a layer of solid phase regrown InGaAs. DEVICE DESIGN AND FABRICATION 2” p-type InP wafers were used as starting substrates, on which a 1 μm p-type In0.53Ga0.45As (Be-doped, doping concentration NA of 2×10 16 cm) was grown. Si ion implant (1×10 cm at 25 keV and 1×10 cm at 70 keV) and mesa etching was done to form n InGaAs well for forming transfer length method (TLM) test structures. Active contact regions were opened by Photoresist (PR) patterning. Ni (~30nm) was deposited and lift-off was done to form contact pads. The 1 Rapid Thermal Anneal (RTA) at 250 ̊C for 30 s forms Ni-InGaAs contact on the n-InGaAs well. The complete process flow for TLM device fabrication is illustrated in Fig. 1(a). The key steps to form NiGe contact is illustrated in Fig. 1(b) where Ge (~70 nm) was evaporated on the Ni-InGaAs pad by lift-off after a 1 min DHF (HF:H2O=1:100) clean. The process was completed by the 2 annealing at various temperatures for 10s. Blanket samples were also prepared for the study of the solid state reaction between Ge and Ni-InGaAs at temperatures ranging from 300 ̊C to 600 ̊C. RESULTS AND DISCUSSION The Secondary Ion Mass Spectroscopy (SIMS) analysis in Fig. 2 shows the elemental distributions of Ni and Ge for as-deposited sample and annealed samples. Similar to as-deposited sample, there is little reaction between Ge and Ni-InGaAs at 300 ̊C as seen from the sharp interface between Ge and Ni signal. However, after 400 ̊C anneal, Ge intermixes with Ni to form a layer of NiGe compound. Therefore, we further studied samples annealed above 300 ̊C in TLM samples. Fig. 3 shows the sheet resistance measured by micro-four-point-probe. The sheet resistance of formed metal layer reduces dramatically after thermal annealing compared with NiInGaAs. TLM test structures were used to evaluate the contact resistance. Fig. 4(a) plots the total resistance versus contact spacing between two adjacent pads. RC for each split is statistically summarized by the box chart in Fig. 5. The control is Ni-InGaAs samples without Ge deposition. On the average, RC is reduced by 64% for samples annealed at 600 ̊C for 10 s. Fig. 6 shows the SIMS signals for samples annealed at 400 ̊C. From the Ge and Ni distributions, it is clear that the top layer consists of a nickel-germanium compound and the sublayer is unconsumed Ni-InGaAs alloy. This was also confirmed by the cross-sectional TEM images of the formed layer in Fig. 7. Fig. 7(b) is the magnified view of the contact materials with EnergyDispersive X-Ray Spectroscopy (EDX) results labeled, showing two metal layers: a top NiGe layer (~66 nm) over a Ni-InGaAs layer (~27 nm). ~24 nm InGaAs regrew at this anneal temperature. It is calculated that the Ge/Ni-InGaAs reaction ratio is around 1.94~2.36. Fig. 8 shows that at 600 ̊C, Ge fully consumes the Ni-InGaAs to form only NiGe on top. TEM images of this condition in Fig. 9 show that the NiGe (~57 nm) layer and the solid phase regrown InGaAs (~49 nm) below the contact material. The NiGe film is continuous and smooth though interface over growth of NiGe was observed at a few spots. Phase identification was carried out using X-Ray diffraction (XRD) in θ-2θ geometry. The XRD spectra in Fig. 10 for annealed samples shows that, for annealing temperatures above 400 ̊C, mono nickel germanide is the dominant phase formed. The surface morphology was characterized by Scanning Electron Microscope (SEM) (Fig. 11). Relatively smooth surface was observed for 400 ̊C and 600 ̊C, while the 500 ̊C sample has a rougher surface. Table I is a summary of the two contact schemes. The novel contact scheme in this work shows superior properties to that of Ni-InGaAs. Future work is needed to integrate this contact technology into InGaAs nMOSFETs in a self-aligned manner. CONCLUSION Solid state reaction between Ge and Ni-InGaAs was demonstrated for the first time on In0.53Ga0.47As substrate. Electrical data from TLM structures shows significant RC reduction. The reaction starts at temperatures above 300 ̊C. The contact material formed is found to be mono nickel germanide. Solid phase regrowth of InGaAs was also observed during the reaction. This novel contact formation scheme could be a promising self-aligned contact for InGaAs nMOSFETs. ACKNOWLEDGEMENT. Support from H.-Y. Lin, C.-H. Ko and C. Wann of TSMC is acknowledged. REFERENCES [1] M. Radosavljevic et al., IEDM Tech. Dig, pp. 126, 2010. [2] R. J. W. Hill et al., IEDM Tech. Dig, pp. 130, 2010. [3] A. Ali. et al., IEDM Tech. Dig, pp. 134, 2010. [4] A. Nainani et al., IEDM Tech.. Dig., pp. 138, 2010. [5] X. Zhang et al., ESL, vol. 14, no. 2, pp. H60, 2011. [6] S. H. Kim et al., IEDM Tech. Dig., pp. 596, 2010. [7] X. Zhang et al., ESL, vol. 14, no. 5, pp. H212, 2011. -608Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials, Nagoya, 2011, pp608-609 A-8-5

III–V MOSFETs: Surface passivation for gate stack, source/drain and channel strain engineering, self-aligned contact metallization

In this paper, we discuss the research and development of several key process modules for realizing high-mobility III–V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III–V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (S/D) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering. InGaAs FETs with high-stress liner stressor were also realized. A CMOS-compatible salicide-like process was developed for self-aligned contact metallization. We also explore the integration of III–V on Si platform for potential device integration.