François Stas

Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes

In the context of wireless sensor nodes for the Internet-of-Things, there is a need for low-power high-performance computing cores for video monitoring applications. In this paper we present a custom 50MHz 32-bit microcontroller running at 0.37V built on a 65nm LP/GP CMOS process. Part of an energy-harvesting SoC with on-chip CMOS imager, it features adaptive voltage scaling, low-power 1.55μW sleep mode, and a variable-width SIMD pipeline and multiply/divide unit, achieving 7.7μW/MHz overall.

SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape

We propose a UWB transmitter (TX) SoC designed for ultra-low voltage (ULV) in 28nm FDSOI CMOS. Operated at 0.55V, it achieves a record energy efficiency of 14pJ/bit with embedded power management (PM), highly duty cycled digital baseband, programmable pulse shaping and wide-range on-chip adaptive forward back biasing (FBB) for VT reduction, PVT compensation and tuning of both the carrier frequency (CF) and the output power.

Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools

The design of analog blocks is a bottleneck in a mixed-signal system designs due to the time-consuming layout step needing human intervention at each iteration of the optimization phase. In this paper, we propose a global automatic sizing and layout integrated methodology for analog block sizing including post-layout verification. The proposed optimizer is based on commercial digital place and route tools for the layout step and does not require custom layout procedures or dedicated layout-template framework. An analog cell library in LEF format with transistor, resistance and capacitance layout is used by the PnR tool allowing placement and routing of these elements. A post-layout netlist with parasitic resistances and capacitances as well as proximity effects is then extracted from generated the GDS file for post-layout simulation. A genetic algorithm is implemented as an optimization kernel allowing automatic sizing iteration. The optimizer is demonstrated in an advanced 28nm FDSOI process on typical analog blocks (two-stage basic amplifier, low-noise amplifier, ΔVT voltage reference and digital-controller oscillator).

Investigation of the routing algorithm in a De Bruijn-based NoC for low-power applications

The De Bruijn topology, due to its interesting features such as a small minimal path, a small average latency and a small average number of hops, is a promising alternative topology to mesh-based NoCs for low-power applications. However, these advantages strongly depend on the efficiency of the routing algorithm in presence of congestion. This paper investigates efficient implementations of routing algorithms in NoCs based on the De Bruijn topology. Four routing algorithms are proposed and evaluated for NoCs up to 64 nodes. Simulation results show that combining FIFO buffers and Deviation Priority in the General Shifting based Routing Algorithm “GSRA” leads to the best performances. With the proposed routing algorithm, the De Bruijn-based NoCs up to 64 nodes are shown to keep excellent communication bandwidth and latency with packet injection rates above 10%. The average number of hops is significantly smaller than for corresponding mesh-based NoC, thereby making the De Bruijn topology an excellent candidate for low-power applications.

Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes

Ultra-low-power (ULP) diodes are special 2-T structures featuring a unique negative-differential resistance characteristic that can be used to build a 4-T ULP latch for flip-flop or SRAM applications. In this paper, we explore the area/mismatch tradeoff in such a ULP latch for ultra-low-voltage (ULV) SoCs in 28 nm FDSOI CMOS. We analyze the impact of transistor sizing, supply voltage and back-gate biasing to reach 6¿ robustness of the latch against mismatch while maintaining a leakage power below 10 pW. Under these constraints, the use of a genetic algorithm allows us to obtain the Pareto curve of optimal solutions between area and speed for both flip-flop and SRAM applications.

Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits

Ultra-low-voltage (ULV) operation of logic circuits is an interesting solution to reduce power consumption in digital circuits. However the always-on blocks at nominal Vdd are necessary for functionality or I/O communications, which induces complex timing closure. In this paper, we propose a 5.4fJ/cycle 0.4V to 1.2V level-shifting flip-flop in 28nm FDSOI, which simplifies the clock tree constraints between the power domains.

A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS

In this paper, we propose an 18-transistor (18T) True-Single-Phase-Clock (TSPC) Flip-Flop (FF) with static data retention based on two forward-conditional feedback loops, without increasing the clock load, in comparison to the baseline TSPC architecture. The proposed FF was implemented for ultra-low-voltage (ULV) operation in 28nm FDSOI CMOS. The performances of the proposed FF extracted from measurements of clock dividers are compared to reference designs including the conventional M-S FF, the baseline TSPC FF and a recently-proposed retentive TSPC FF. Compared to the conventional MS FF, the proposed FF shows respectively 5%, 60% and 30% improvements at 0.4V in maximum frequency, energy/cycle and leakage power.

Automated layout-integrated sizing of a 2.45 GHz differential-drive rectifier in 28 nm FDSOI CMOS

Rectifiers are considered key analog blocks to power the energy-autonomous wireless applications envisioned by the Internet-of-Things. However, their design routine is still a time-consuming process as the layout step requires human intervention at each iteration of the optimization phase. The layout parasitic effects (e.g. well-proximity effects) introduced by this step can have a non-negligible impact on circuit performances, especially when targeting high-efficiency operation at UHF in the ultra-low power range, where parasitics have a higher impact. In this paper, we propose an automatic sizing and layout integrated methodology, based on commercial digital place and route tools, to optimize the cross-coupled/differential-drive rectifier architecture, including post-layout verification, in an advanced 28nm FDSOI CMOS process. A genetic and a gradient optimization methods are compared to increase the time-efficiency of the methodology. A 3-stage rectifier is optimized, providing 1.17 μW under 1 μΑ load at 2.45 GHz with 68% efficiency.

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation

In this paper, we propose an ultra-low-voltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low Vt (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB macro. Process voltage temperature (PVT) compensation is performed on-chip by an adaptive back biasing (ABB) generator. At 0.4V, the proposed SRAM can operate at 80 MHz and reaches access energy of 28 fJ/bit including the ABB generator in closed-loop operation.

SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping

Achieving wireless communications at 5–30 Mb/s in energy-harvesting Internet-of-Things (IoT) applications requires energy efficiencies better than 100 pJ/b. Impulse-radio ultrawideband (UWB) communications offer an efficient way to achieve high data rate at ultralow power for short-range links. We propose a digital UWB transmitter (TX) system-on-chip (SoC) designed for ultralow voltage in 28-nm FDSOI CMOS. It features a PLL-free architecture, which exploits the duty-cycling nature of impulse radio through aggressive duty cycling within the pulse modulation time slot for high energy efficiency and minimum jitter accumulation. Wide-range on-chip adaptive forward back biasing is used for threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. To ensure spectral compliance with output power regulations without the use of bulky and expensive off-chip filters, a programmable pulse-shaping functionality is integrated in the digital power amplifier based on a 7–9-GS/s, 5-b current DAC. Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the TX alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.