Pierre-Olivier Jeannin

Comparison of Junction Temperature Evaluations in a Power IGBT Module Using an IR Camera and Three Thermosensitive Electrical Parameters

The measurement of the junction temperature with thermosensitive electrical parameters (TSEPs) is largely used by electrical engineers or researchers, but the obtained temperature value is generally not verified by any referential information of the actual chip temperature distribution. In this paper, we propose to use infrared (IR) measurements in order to evaluate the relevance of three commonly used TSEPs with insulated gate bipolar transistor chips: the saturation voltage under a low current, the gate-emitter voltage, and the saturation current. TheIR measurements are presented in detail with an estimation of the emissivity of the black paint deposited on the power module. The temperatures obtained with IR measurements and with the different TSEPs are then compared in two cases: the use of only one chip and the use of two paralleled chips.

Original cabling conditions to insure balanced current during switching transitions between paralleled semiconductors

This paper deals with the problem of paralleling components. First, general investigations concerning the influence of stray inductances on the current and voltage differences between n paralleled components are presented. Original cabling conditions are deduced to insure balanced electrical constraints. Then, a power module involving two paralleled MOSFETs is analysed. To validate the original presented conditions, two different choppers, involving paralleled power modules have been built, with different layouts. Experimental and simulated results confirm the validity of the proposed rules.

Comparison of junction temperature evaluations in a power IGBT module using an IR camera and three thermo-sensitive electrical parameters

The measurement of the junction temperature with thermo-sensitive electrical parameters (TSEPs) is largely used by electrical engineers or researchers but the obtained temperature value is generally not verified by any referential information of the actual chip temperature distribution. In this paper, we propose to use infrared (IR) measurements in order to evaluate the relevance of three commonly used TSEP with IGBT chips: the saturation voltage under a low current, the gate-emitter voltage and the saturation current. The IR measurements are presented in details with an estimation of the emissivity of the black paint deposited on the power module. The temperatures obtained with IR measurement and with the different TSEPs are then compared in two cases: the use of only one chip and the use of two paralleled chips.

Series connection of IGBT

This article analyzes the effects of parasitic capacitances in the series connection of IGBT, which exist naturally due to gate driver and power circuit geometry. Two solutions, that can be combined, are proposed to minimize these effects in order to achieve a better voltage balancing. The first one is based on gate driver self-powering technique. The second one is based on a vertical structure assembly of IGBT connected in series. The performance offered by these two complementary solutions is investigated and validated on a series connection of three IGBT in a chopper converter. Both simulation and experimental results show the effectiveness of our approaches.

1 MHz power factor correction boost converter with SiC Schottky diode

This paper deals with the design of 1 MHz switching frequency boost convert with silicon carbide power Schottky diodes. This application is designed to work as a power factor correction rectifier. With high breakdown voltage, high energy gap and good thermal conductivity, silicon carbide (SiC) is a serious challenger as a new power semiconductor material. Here we analyze switching behavior in order to evaluate losses in such applications. Then, we compare theoretical and experimental results on PFC boost application.

Compact, isolated and simple to implement gate driver using high frequency transformer

This paper presents a simple, ultra-compact and isolated gate driver system used to drive power switches. Using two legs of a CMOS inverter, a high frequency transformer and two zener diodes connected with the gate of power switch, this driver provides an optimal gate driver waveform with a high gate voltage to switch on the transistor, and a negative bias gate voltage during OFF state. In the paper, the proposed gate driver will be theoretically analyzed; simulation and experimental results for the system implemented to drive a high side MOSFET will be also showed and discussed.

Complete Analytical Calculation of Static Leakage Parameters: A Step Toward HF Transformer Optimization

The predetermination of the leakage inductances of transformers is essential for component designers. Except for special winding disposal, the usual analytical methods of evaluation are ineffective, while the finite-element-method simulation evaluation requires too much time to be suitable for any optimization process. In a previous work, we supplied the analytical expression for vector potential from which we deduced leakage inductance through numerical integration. In this paper, an explicit expression of leakage inductances is given. This expression does not appear as a series, requires shorter computing time, and opens up a lot of future applications relying on optimization software. Moreover, the calculation is not restricted to leakage inductances: It has been extended to all the parameters characterizing the whole leakage behavior of any transformer. The influence of ferrite permeability and thickness is also investigated.

Improvement of GaN transistors working conditions to increase efficiency Of A 100W DC-DC converter

GaN transistors can be used instead of Si MOSFET, because they improve static and dynamic performances. Moreover, low power DC-DC converters are often not very efficient, so GaN represents a good solution to improve efficiency. This article presents a comparison between Si MOSFET and GaN HEMT performances by using them in a high frequency isolated DC-DC converter. The structure and his control are described, and the maximum efficiency is higher than 94%. After having highlighted critical points for efficiency, a way to improve working conditions of GaN transistors is investigated. The converter is based on EPC GaN components.

Design and Investigation of an Isolated Gate Driver Using CMOS Integrated Circuit and HF Transformer for Interleaved DC/DC Converter

This paper deals with the design and the implementation of an isolated gate driver system using a CMOS integrated circuit for interleaved dc/dc converters. It is based on a novel gate driver topology for power switches like MOSFETs and insulated-gate bipolar transistors. Composed of two legs of a CMOS inverter, a high-frequency pulse transformer, and two Zener diodes connected in antiseries configuration with the gate of the power switch, this driver topology provides an optimal bipolar gate driver waveform with greater positive and negative gate biases to fasten the switch on and off. It represents a simple ultracompact isolated gate driver simple to integrate in CMOS technology. Power consumption, system size, and robustness of the gate driver are therefore optimized. This integrated driver circuit can be used for any multitransistor applications. We detail the operation principle of the proposed driver topology in this paper. We implemented the gate driver to control a three-phase interleaved boost converter; the results show the effectiveness of the proposed driver system.

A Novel DC Bus Voltage Balancing of Cascaded H-Bridge Converters in D-SSSC Application

This paper introduces a new scheme to balance the DC bus voltages of a cascaded H-bridge converter which is used as a Distribution Static Synchronous Series Compensator (D-SSSC) in electrical distribution network. The aim of D-SSSC is to control the power flow between two feeders from different substations. As a result of different cell losses and capacitors tolerance the cells DC bus voltage can deviate from their reference values. In the proposed scheme, by individually modifying the reference PWM signal for each cell, an effective balancing procedure is derived. The new balancing procedure needs only the line current sign and is independent of the main control strategy, which controls the total DC bus voltages of cascaded H-bridge. The effect of modulation index variation on the capacitor voltage is analytically derived for the proposed strategy. The proposed method takes advantages of phase shift carrier based modulation and can be applied for a cascaded H-bridge with any number of cells. Also the system is immune to loss of one cell and the presented procedure can keep balancing between the remaining cells. Simulation studies and experimental results validate the effectiveness of the proposed method in the balancing of DC bus voltages.