Pinar Basak Basyurt

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18µm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190mV with temperature coefficients of 43ppm/?C and 52.5ppm/?C over the temperature range of 0 to 120?C without any trimming with a 0.8V single supply. The power consumptions of the circuits are less then 500nW while occupying an area of 0.2mm2 and 0.08mm2, respectively.

A 490-nA, 43-ppm/°C, sub-0.8-V supply voltage reference

This paper presents a low power bandgap reference generator with 193-mV output voltage. The nominal supply voltage is 0.8 V, but the circuit can work with a supply down to 0.65 V. The circuit has been fabricated with a standard 0.18 μm CMOS technology and achieves a temperature coefficient of 43 ppm/°C for temperatures ranging from 0 to 120°C. A sampled-data amplifier consuming 140 nA and a reversed current-mode bandgap scheme draining 350 nA enable the achieved performance.

Design of a curvature-corrected bandgap reference with 7.5ppm/C temperature coefficient in 0.35µm CMOS process

This paper presents the design of high-precision curvature-corrected bandgap voltage reference circuit realized in 0.35μm CMOS technology. The circuit generates an output voltage of 500mV with temperature coefficient of 7.5ppm/C over a temperature range of -30C to 120C, with a power supply rejection ratio of 58dB at 100Hz, and an rms output noise of 5.33μV integrated from 0.1Hz to 10Hz. The circuit operates down to 1.8 volts with a line sensitivity of 0.12%/V. The design consumes 9.74μA of supply current, and occupies an area of 0.075mm2.

Sampled-data operational-amplifier with ultra-low supply voltage and sub µW power consumption

This paper proposes the use of sampled-data operation in op-amps. The technique favors very low supply voltage and micro-power. After discussing the method at a general level, a possible sampled-data scheme is analyzed. Simulations with a low threshold technology show that a 0.5-V supply is possible. A version of the circuit, which has been integrated by using a standard 0.18-μm CMOS technology (with high thresholds), is able to operate at 0.65-V supply voltage. Simulation results show 42.5 dB of DC gain and 2.5-kHz bandwidth with 0.5-pF load capacitor. The power consumption is 63 nW. A pseudo-differential scheme doubles the consumed power and increases the DC gain by 6 dB.

CMOS colpitts LC reference oscillator with 70ppm absolute frequency accuracy within 0 – 80 °C

This paper presents design and simulation of two temperature compensated LC Colpitts reference oscillator. First uses an on-chip differential inductor while the other one uses bondwire inductor. Technology is 0.35µm 2P/4M CMOS technology with high resistivity poly and thick metal option. Oscillator with on-chip differential inductor consumes 7.5mA from 2.5V supply and absolute peak frequency deviation is 70ppm within 0–80°C and oscillator with bondwire inductor consumes 1.5mA from 2.5V supply and absolute peak frequency deviation is 150ppm between 0–80°C. Nominal operating frequency is 1.5GHz for both oscillators.

A low-power low-noise CMOS voltage reference with improved PSR for wearable sensor systems

This paper describes a novel sub-threshold voltage reference generator suitable for very low power and very low voltage wearable systems. Indeed, the circuit, designed and extensively simulated in a standard 0.18-μm CMOS technology, generates a 51.3-mV output voltage with a nominal supply voltage of 0.5 V and consumes as low as 185 nW. Design optimisation and a first order temperature compensation allow achieving a temperature coefficient of 25.4 ppm/ C in the temperature range from −40 to 125° C. The proposed architecture optimizes the output noise performance by minimizing the current mirrors flicker and thermal noise contributions which, in conventional schemes, severely affect the output node. In addition, the same circuital arrangement allows obtaining high power supply rejection (PSR). The simulated root mean square output noise is 1.6 μV in the frequency range from 0.1 Hz to 10 Hz, while the PSR is −76 dB at 100 Hz, a remarkable value.

Very-low-voltage and ultra-low-power analog circuits for nomadic applications

This paper gives an overview on the key features of the several building blocks constituting modern nomadic systems. Different micro-power energy harvesting techniques are described and discussed. In addition, this paper reviews the state of the art and provides recently published examples of low power low voltage analog circuits, such as operational amplifiers, reference generators, and data converters.

Design of an op-amp free voltage reference with PWM regulation

This paper presents the design of an op-amp free voltage reference generator which utilizes a pulse width regulated loop. The proposed voltage reference circuit has been designed and simulated in a standard 0.18-μm CMOS technology. Post layout simulation results show that it is capable of operating with supply voltages down to 0.7 V while generating an output voltage of 202 mV. The achieved temperature coefficient is 54 ppm/°C for temperatures ranging from 0 to 100 °C. The simulated power consumption at the room temperature is 400 nW.

Frequency synthesis using pulse width locked loop

Implemented fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for δΣ Modulator within the loop while preserving the frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the designer to optimize the synthesizer loop bandwidth without any constraint imposed by the modulator. The loop operates by locking precisely the output frequency to a control voltage. Implemented loop occupies an area of 650µm by 630µm in 0.35µm CMOS process and draws 383µA from a single 3.3V supply. It covers a frequency range of 4–70MHz with 76Hz resolution and has a measured phase noise performance of 104dBc/Hz at 1MHz offset with the worst spurious signal level of −70dBc.