Edoardo Bonizzoni

4-Mb MOSFET-selected phase-change memory experimental chip

This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator

The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.

SET and RESET pulse characterization in BJT-selected phase-change memories

This paper presents program pulse characterization in an 8-Mb BJT-selected phase-change memory test chip. Experimental results of the impact of the bit-line resistance over programming pulse efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter

A single-inductor dual-output DC-DC buck converter is presented. The inductor, which is external, provides two independent output voltages ranging from 1.2V to the power supply with a maximum total output current of 200mA. The supply can range from 2.6 to 5V. The converter is fabricated in a 0.35mum p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved and the efficiency is always >62.5%.

A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current

Minimizing power consumption in multi-processor systems requires the use of multiple supplies with a wide range of regulated voltages and currents. Since one inductor per DC-DC converter is expensive, there is an increasing interest in single-inductor-multiple-output (SIMO) DC-DC converters. Recent research results report a SIMO boost converter and various boost or buck converters with two outputs. This 0.5mum CMOS system is a four- output, single-inductor buck converter with independent regulation of each output.

A fully symmetrical sense amplifier for non-volatile memories

This paper presents a fully symmetrical sense amplifier topology for advanced non-volatile memories. The proposed structure ensures zero systematic offset, together with adequate rejection of disturbs coming from capacitive coupling with noisy substrate, power supply, and ground. The presented topology has been designed for phase change memories, however, it is also suitable for use in other non-volatile storage devices such as magnetic RAMs and Flash memories. Experimental results on sensing time, offset, and sensitivity demonstrated the effectiveness of the proposed scheme.

4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

A /spl mu/trench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-/spl mu/m CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.

On the design of single-inductor multiple-output DC-DC buck converters

Design techniques for single inductor multiple output (SIMO) DC-DC buck converters are presented. The suitable control of a multiple feedback loop enables the sharing of a single inductor with many outputs with a good stability and limited cross regulation. The method has been verified with simulations at the behavioural and transistor level to obtain four independent regulated output voltages ranging from 0 V to 1 V below the power supply voltage. The use of a suitable analog processing of errors allows obtaining a power efficiency as high as 86%.

Slew-rate and gain enhancement in two stage operational amplifiers

A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 µm technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/µs slew-rate for a load capacitance of 1.75 pF with 362 µW power consumption, considering a supply voltage of 1.8 V.

A Micropower Chopper—CDS Operational Amplifier

A low-power spur-free precision amplifier, which uses input chopping and correlated double sampling for demodulation, is presented. This circuit employs an AC coupling between the first and the second stage that removes the first stage offset without causing ripple. The input rail-to-rail circuit, fabricated in a mixed 0.18-0.5 μm CMOS technology, operates with supply ranging from 1.8 V to 5 V. The circuit achieves a simulated 168-dB DC gain with an overall current consumption of 14.4 μA. The measured offset voltage over the available samples results in a distribution with 2-μV standard deviation. The obtained input noise density at low-frequency equal to 37 nV/√Hz gives a 5.5 noise efficiency factor.