Ping-Chih Chang

InGaP/InGaAsN/GaAs NpN double-heterojunction bipolar transistor

The authors have demonstrated a functional NpN double heterojunction bipolar transistor (DHBT) using InGaAsN for base layer. The InGaP/In{sub 0.03}Ga{sub 0.97}As{sub 0.99}N{sub 0.01}/GaAs DHBT has a low V{sub ON} of 0.81 V, which is 0.13 V lower than in a InGaP/GaAs HBT. The lower V{sub ON} is attributed to the smaller bandgap (E{sub g}=1.20eV) of MOCVD grown In{sub 0.03}Ga{sub 0.97}As{sub 0.99}N{sub 0.01} base layer. GaAs is used for the collector; thus the BV{sub CEO} is 10 V, consistent with the BV{sub CEO} of InGaP/GaAs Hbts of comparable collector thickness and doping level. To alleviate the current blocking phenomenon caused by the larger {triangle}E{sub C} between InGaAsN and GaAs, a graded InGaAs layer with {delta}-doping is inserted at the base-collector junction. The improved device has a peak current gain of 7 with ideal IV characteristics.

InGaAsN/AlGaAs P-n-p heterojunction bipolar transistor

We have demonstrated a functional P-n-p heterojunction bipolar transistor (HBT) using InGaAsN. The metalorganic-vapor-phase-epitaxy-grown Al0.3Ga0.7As/In0.03Ga0.97As0.99N0.01 HBT takes advantage of the narrower band gap energy (Eg=1.2 eV) of In0.03Ga0.97As0.99N0.01, which is lattice matched to GaAs. Compared with the Al0.3Ga0.7As/GaAs material system, the Al0.3Ga0.7As/In0.03Ga0.97As0.99N0.01 material system has a larger conduction-band offset, while the valence-band offset remains comparable. This characteristic band alignment is very suitable for P-n-p HBT applications. The device’s peak current gain is 23, and it has a turn-on voltage of 0.77 V, which is 0.25 V lower than in a comparable P-n-p Al0.3Ga0.7As/GaAs HBT.

Effect of Mg ionization efficiency on performance of Npn AlGaN/GaN heterojunction bipolar transistors

A drift-diffusion transport model has been used to examine the performance capabilities of AlGaN/GaN Npn heterojunction bipolar transistors (HBTs). The Gummel plot from the first GaN-based HBT structure recently demonstrated is adjusted with simulation by using experimental mobility and lifetime reported in the literature. Numerical results have been explored to study the effect of the p-type Mg doping and its incomplete ionization in the base. The high base resistance induced by the deep acceptor level is found to be the cause of limiting current gain values. Increasing the operating temperature of the device activates more carriers in the base. An improvement of the simulated current gain by a factor of 2 to 4 between 25 and 300 C agrees well with the reported experimental results. A preliminary analysis of high frequency characteristics indicates substantial progress of predicted rf performances by operating the device at higher temperature due to a reduced extrinsic base resistivity.

Significant operating voltage reduction on high-speed GaAs-based heterojunction bipolar transistors using a low band gap InGaAsN base layer

We report the fabrication of double heterojunction bipolar transistors (DHBTs) with the use of a new quaternary InGaAsN material system that takes advantage of a low-energy band gap E/sub G/ in the base to reduce operating voltages in GaAs-based electronic devices. InGaP/In/sub 0.03/Ga/sub 0.97/As/sub 0.99/N/sub 0.01//GaAs DHBTs with improved band gap engineering at both heterojunctions exhibit a DC peak current gain over 16 with small active emitter area. The use of the lattice-matched In/sub 0.03/Ga/sub 0.97/As/sub 0.99/N/sub 0.01/ (E/sub G/=1.20 eV) base layer allows a significant reduction of the turn-on voltage by 250 mV over standard InGaP/GaAs HBTs, while attaining good high-frequency characteristics with cutoff frequency and maximum oscillation frequency as high as 40 GHz and 72 GHz, respectively. Despite inherent transport limitations at the present time, which penalize peak frequencies, this novel technology provides comparable RF performance to conventional devices with a GaAs control base layer but at much lower operating base-emitter bias conditions. This technical progress should benefit to the next generation of RF circuits using GaAs-based HBTs with lower power consumption and better handling of supply voltages in battery-operated wireless handsets.

Simulation of npn and pnp AlGaN/GaN heterojunction bipolar transistors performances: limiting factors and optimum design

The performance capabilities of npn and pnp AlGaN/GaN heterojunction bipolar transistors have been investigated by using a drift-diffusion transport model. Numerical results have been employed to study the effect of the p-type Mg doping and its incomplete ionization on device performance. The high base resistance induced by the deep acceptor level is found to be one of the causes of limited current gain values for npn devices. Reasonable improvements of the dc current gain /spl beta/ are observed by realistically reducing the base thickness and consequently the transit time, in accordance with processing limitations. Base transport enhancement is predicted by the introduction of a quasi-electric field in the base. The impact of the base resistivity on high-frequency characteristics is investigated for npn AlGaN/GaN devices. Simulation results reveal the difficulty to achieve decent current gain values at high current density for pnp HBTs in common emitter configuration. Despite the high electron mobility in the n-type base that aids in reducing the base resistance, a preliminary analysis for pnp devices indicates limited rf performances caused by the reduced minority hole transport across the base.

Device characteristics of the GaAs/InGaAsN/GaAs p-n-p double heterojunction bipolar transistor

We have demonstrated the dc and rf characteristics of a novel p-n-p GaAs/InGaAsN/GaAs double heterojunction bipolar transistor. This device has near ideal current-voltage (I-V) characteristics with a current gain greater than 45. The smaller bandgap energy of the InGaAsN base has led to a device turn-on voltage that is 0.27 V lower than in a comparable p-n-p AlGaAs/GaAs heterojunction bipolar transistor. This device has shown f/sub T/ and f/sub MAX/ values of 12 GHz. In addition, the aluminum-free emitter structure eliminates issues typically associated with AlGaAs.

A 0.25

Static frequency dividers are widely used technology performance benchmark circuits. Using a 0.25 μm 530 GHz fT /600 GHz+ fmax InP DHBT process, a static frequency divider circuit has been designed, fabricated, and measured to operate up to 200.6 GHz. The divide-by-two core flip-flop dissipates 228 mW. Techniques used for the divider design optimization and for selecting variants to maximize performance across process changes are also discussed.

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An air-stable electronic surface passivation for GaAs and other III–V compound semiconductors that employs sulfur and a suitable metal ion, e.g., Zn, and that is robust towards plasma dielectric deposition has been developed. Initial improvements in photoluminescence are twice that of S-only treatments and have been preserved for >11 months with SiOxNy dielectric encapsulation. Photoluminescence and x-ray photoelectron spectroscopies indicate that the passivation consists of two major components with one being stable for >2 years in air. This process improves heterojunction bipolar transistor current gain for both large and small area devices.

m InP DHBT 200 GHz+ Static Frequency Divider

Abstract A current gain β of 23 is demonstrated from a small-area NpN GaAs-based double heterojunction bipolar transistor (HBT) using a low band-gap InGaAsN material (lattice matched to GaAs with an energy band gap EG of 1.2 eV) as the base layer. An improved band-gap engineering design at both emitter–base and base–collector heterojunctions in this GaAs-based HBT structure allows significant turn-on voltage reduction up to 270 mV compared to conventional InGaP/GaAs HBTs, while attaining high-speed performance. Self-aligned devices with emitter active area of 3×5 μm2 show cutoff frequency fT and maximum oscillation frequency fMAX values of 32 and 52 GHz, respectively. These results demonstrate the strong potential of this novel HBT technology to reduce power consumption in future wireless handsets using the GaAs manufacturing platform.

Metal-sulfur-based air-stable passivation of GaAs with very low surface-state densities

Static dividers are well recognized performance benchmarks for mixed-signal technologies. We report an emitter-coupled logic (ECL) static divider with a maximum operating frequency of 154.75 GHz. The same divider was demonstrated to operate down at 5 GHz at the same bias, dissipating 222.11 mW. The circuit was fabricated in a high performance 0.25-pm InP DHBT technology withfT> 300 GHz andfmax > 450 GHz. We discuss device, processing, and circuit design. The InP/InGaAs/InP double HBTs were grown by solid source molecular beam epitaxy. The HBT layer structure includes an InP emitter, a 300-A compositionally graded InGaAs base doped with beryllium at 8x1019cmM3, and a 1200-A InP collector. After HBT fabrication, the devices were planarized with a spin-on dielectric, and vias were etched down for the emitter, base, and collector contacts. The backend process included thin-film resistors, metal-insulator-metal capacitors, 4 levels of planarized interconnect on low-K dielectric, and optional back-side thinning / vias / metallization. Figure 1 shows the cross-section of a finished HBT with a 0.25-ptm emitter and a segment of a circuit with 4 levels of interconnect. HBTs were fabricated with emitter widths as small as 0.14 ptm; however, scaling effects related to the base contact width caused the 0.25-ptm HBTs to give the best high-frequency performance. Typical current gain (P) is between 20 and 30, and the breakdown voltage (BVCEO) is 4 V. The HBT is designed for peak RF performance at a moderately high JE = 7 mA/ tm2 (see Figure 2). Peak fT 322 GHz occurs at VCB 0.27 V when the collector is partially undepleted for reduced transit time, and peakfmax 459 GHz occurs at VCB 0.78 V when the collector is fully depleted and CBC is minimized. Figure 3 illustrates the major blocks of our static divider. Static divider design in the D-Band regime poses many challenges. First, transistors operating at such high frequencies in ECL topologies are prone to oscillation. Next, the time constants at the latch load nodes can limit high-speed performance. Capacitances from conventional, transistor current sources begin to become limiting time constants as well. The interface circuitry to and from the actual divider core must be carefully designed to not mask core performance. Input reflections and circuit bandwidth make it challenging for the input path to provide adequate power and slew rate to switch the core. Today, D-Band sources are single-ended, where headroom can also limit the maximum signal level delivered to the core. The divider core output must contend with the parasitic capacitance of the feedback path as well as the loading of subsequent output stages. Employing high bandwidth circuit techniques can sometimes be detrimental to low frequency performance, further exacerbating the challenge of static divider design. Finally, power must be considered for practical systems. Each of the mentioned challenges was addressed in the divider design. The divider was stabilized by covering most of the circuit with a ground plane. We found it to be a more optimal tradeoff between stability and bandwidth compared to other techniques, such as inserting damping resistors at base terminals. Inductive peaking was used to improve the time constant at the latch load nodes. Resistors were used for all current sources in the circuit to reduce current source capacitance. A broadband input matching network was designed and optimized to minimize reflections and maximize power delivered to the divider core. The layout floorplan of the divider core was such that the inter-latch signals are perpendicular to the main divider signal flow, resulting in a relatively short divider feedback interconnect path. Relatively large resistances were inserted between the core and output stages to alleviate core capacitive loading. Careful selection and iterative evaluation of devices, resistors, and inductances was required to achieve simultaneous high and low frequency performance, i.e., static performance. We found emitter resistance to be a key device limiter in static performance. Power can be substantially reduced in a currentsteering latch topology by removing emitter followers (EF). However, this results in non-optimal base-collector biasing of the switching and regenerative latch pairs. Realizing that JE of the EF is the key for high frequency performance, the supply voltage on the EF was reduced while maintaining the same JE. This results in much lower power dissipation than if the EF were biased at the same supply voltage as the switching and regenerative pairs. Divider testing done in the V, W, and D-bands were done with a diode quadrupler or backward-wave oscillator (BWO) and harmonic mixers. A conventional RF signal generator was used for testing at 50 GHz and below. Measured divider performance is illustrated at 154.75 GHz and 5 GHz in Figure 4 and Figure 5, respectively. Our 154.75 GHz device was damaged during testing so we were only able to obtain a sensitivity plot from another site in the same wafer that operated from 10 GHz to 151 GHz (see Figure 6).