Pit-Leong Wong

Investigation of candidate VRM topologies for future microprocessors

By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation high-speed complementary metal-oxide-semiconductor (CMOS) processors (e.g., Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range, to further enhance their speed-power performance. These new generation microprocessors will present very dynamic loads with high current slew rates during transient. As a result, they will require a special power supply, voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. In this paper, the critical technical issues to achieve this target for future generation microprocessors are addressed. A VRM candidate topology, interleaved quasisquare-wave (QSW), is proposed. The design, simulation and experimental results are presented.

Performance improvements of interleaving VRMs with coupling inductors

The multichannel interleaving buck converter with small inductance has proved to be suitable for voltage regulator modules (VRMs) with low voltages, high currents, and fast transients. Integrated magnetic components are used to reduce the size of the converter and improve efficiency. However, the structure of the integrated magnetic requires precise adjustment and is not mechanical stable. This paper proposes integrated coupling inductors between the channels to solve these problems. With the proper design, coupling inductors can improve both the steady-state and dynamic performances of VRMs with easier manufacturing.

A novel integrated current doubler rectifier

This paper presents an innovative current doubler rectifier, which integrates all the magnetic components into a single core and minimizes the number of high current windings. Compared to the conventional approach, the proposed integrated magnetic structure features reduced core loss, smaller core size, and reduced AC conduction losses, all while still reducing winding losses. The new rectification circuit can be applied to many topologies. An asymmetrical half-bridge converter was used as one attractive example to demonstrate the operation and performance of the proposed structure. A prototype featuring 400 V input, 48 V output, 200 kHz switching frequency, and 1 kW output power was also developed based on this topology.

Investigating coupling inductors in the interleaving QSW VRM

The multi-channel interleaving quasi-square-wave (QSW) buck converter has been proved to be suitable for the voltage regulator module (VRM) with low voltage, high current and fast transient response. Integrated magnetic is used to reduce the size of the converter and improve efficiency. However, the structure of the integrated magnetic requires precise adjustment. In this paper, analysis shows that a properly designed integrated magnetic can improve the steady-state and dynamic performance without requiring precise adjustment.

VRM transient study and output filter design for future processors

In this paper, the transient response of the (voltage regulator module) VRM output voltage when the processor has a fast load change is analyzed. The parasitic parameters play important roles in the transient. The system can be divided into several resonant loops. Each loop can be approximately considered as a decoupled second order system. The transient response is affected by the magnitude of the load change rather than the slew rate of it. Limitations of the present VRM topology for future specifications and output filter design are discussed.

Quasi-square-wave rectification for front-end DC/DC converters

In the front-end DC/DC converters, the secondary rectification contributes an important part of loss. This paper investigates using synchronous rectified working in quasi-square-wave (QSW) mode to reduce both the conduction and reverse recovery loss in the secondary side. QSW can also help the soft-switching of the primary switches. A 1 kW half-bridge converter is built to verify this idea. Efficiency higher than 95% can be achieved for most of the load range for 100 kHz operation.

Investigation of candidate VRM topologies for future microprocessors [voltage regulator modules]

Future generation microprocessors are expected to exhibit much heavier loads and much faster transient slew rates. Todays voltage regulator module (VRM) will need a large amount of extra decoupling and output filter capacitors to meet future requirements, which basically makes the existing VRM topologies impractical. In this paper, a candidate topology, interleaved quasi-square wave, is proposed. Its design, simulation and experimental results are presented.