Xunwei Zhou

Investigation of candidate VRM topologies for future microprocessors

By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation high-speed complementary metal-oxide-semiconductor (CMOS) processors (e.g., Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range, to further enhance their speed-power performance. These new generation microprocessors will present very dynamic loads with high current slew rates during transient. As a result, they will require a special power supply, voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. In this paper, the critical technical issues to achieve this target for future generation microprocessors are addressed. A VRM candidate topology, interleaved quasisquare-wave (QSW), is proposed. The design, simulation and experimental results are presented.

A novel current-sharing control technique for low-voltage high-current voltage regulator module applications

Future generations of microprocessors are expected to exhibit much heavier loads and much faster transient slew rates. Todays voltage regulator module (VRM) will need a large amount of extra decoupling and output filter capacitors to meet future requirements, which will basically make the existing VRM topologies impractical. As a candidate topology, the interleaved quasisquare-wave (QSW) VRM exhibits very good performance, such as a fast transient response and a very high power density. The difficulty with the application of the interleaved parallel technology is the current-sharing control. In this paper, a novel current-sensing and current-sharing technique is proposed. With this technique, current sharing can be controlled simply in parallel converters without a current transformer and current-sensing resistors. In addition, this technique can be easily integrated with an IC chip. The four-module paralleled QSW VRM is used to evaluate this technique. Experimental results verify that with this technique, the VRM has a high power density, high efficiency and a fast transient response. The concept of the current sharing technique is also generalized and extended.

Improved light-load efficiency for synchronous rectifier voltage regulator module

DC/DC converter with high efficiency over a wide load range is necessary for many low voltage applications, such as battery supplied systems and micro-processor power supplies-voltage regulator module (VRM). In order to improve the efficiency of low voltage converters, synchronous rectifier technology is widely used. The disadvantage of this technology is low efficiency at light load. This paper proposes a new technology, which utilizes the duty cycle signal, to improve light load efficiency with simple implementation. Since current sensors are not required, high density and high efficiency can be achieved that makes the whole circuit suitable for integration. In the paper, two application examples are given. Experimental results verified that the proposed control schemes significantly improve the efficiency of synchronous rectifier buck converters at light load.

Integrated planar inductor scheme for multi-module interleaved quasi-square-wave (QSW) DC/DC converter

Compact, high-efficiency, low-voltage and large-current DC/DC power converters with a fast transient slew rate are needed for future generation microprocessors. The interleaved quasi-square-wave (QSW) topology is a good candidate to improve their transient response significantly. Inductors are critical components in these converters. An integrated planar inductor scheme for multi-module interleaved QSW power converters is proposed. This integrated inductor utilizes the phase relationships of the currents in each module to integrate all the separate inductors for each module into one core, resulting in great reductions in the size and power losses of the inductor.

Single shot transient suppressor (SSTS) for high current high slew rate microprocessor

Future generation microprocessors are predicted to exhibit heavier loads and faster transients. Conventional voltage regulator modules (VRM) need a large amount of output filter capacitors to meet future requirements and a huge number of decoupling capacitors, mainly due to the presence of parasitic inductance between the VRM and the microprocessor. In this paper, a new active damp concept is presented. By charging some auxiliary capacitors at higher voltage, it is possible to store the amount of charge required by the processor during the step up transient; this extra charge can be locally delivered to the processor in a single shot manner, bypassing the slower VRM. In the same way, this circuit can sink the excess of charge that has to be removed during the step down transient. By using this transient suppressor circuit, a conventional VRM can still provide adequate steady state regulation, while the size of decoupling and filter capacitors can be significantly reduced. Experimental results prove the validity of the concept.

A high power density, high efficiency and fast transient voltage regulator module with a novel current sensing and current sharing technique

Future generations of microprocessors are expected to exhibit much heavier loads and much faster transient slew rates. Todays voltage regulator module (VRM) will need a large amount of extra decoupling and output filter capacitors to meet future requirements, which basically makes the existing VRM topologies impractical. As a candidate topology, the interleaved quasi-square-wave (QSW) exhibits very good performance, such as fast transient response and very high power density. The limitation in the application of the interleaved parallel technology is current sharing control. In this paper, a novel current sensing and current sharing technique is proposed. With this technique, current sharing can be controlled simply in parallel converters without current transformer and current sensing resistors. Experimental results verify that with this technique, a 4-module interleaved QSW VRM has high power density, high efficiency and fast transient response.

VRM transient study and output filter design for future processors

In this paper, the transient response of the (voltage regulator module) VRM output voltage when the processor has a fast load change is analyzed. The parasitic parameters play important roles in the transient. The system can be divided into several resonant loops. Each loop can be approximately considered as a decoupled second order system. The transient response is affected by the magnitude of the load change rather than the slew rate of it. Limitations of the present VRM topology for future specifications and output filter design are discussed.

Improved zero-current transition converters for high power applications

Existing zero-current transition (ZCT) converters do not solve main switch turn-on problems and require auxiliary switches to be turned off with high current, and therefore are not suitable for high power applications. Novel ZCT schemes proposed in this paper enable all main switches and auxiliary switches to be turned on and off under zero current conditions. The zero-current switching at both turn-on and turn-off not only reduces switching losses significantly, but also eliminates the necessity of passive snubbers due to the much reduced switch stress. The cost of the auxiliary switches can be reduced compared to the existing ZCT schemes due to their zero-current turn-off. The proposed technology is well suited for DC-DC and three-phase converters with IGBTs, MCTs and GTOs. Theoretical analysis, computer simulation and experimental results are presented to explain the proposed schemes.

Improve light load efficiency for synchronous rectifier buck converter

A DC/DC converter with high efficiency over very wide load range is necessary for many low voltage applications, such as battery supplied systems and microprocessor power supplies-voltage regulator module (VRM). In order to improve the efficiency of low-voltage power converters, synchronous rectifier technology is widely used. The disadvantage of this technology is low efficiency at light load. This paper proposes a new technology that can improve light load efficiency with very simple implementation. Since current sensors are not required, high density and high efficiency can be achieved that makes the whole circuit suitable for integration. In the paper, two application examples are given. Experimental results verified that this technology significantly improves synchronous rectifier buck converters light load efficiency.

Low voltage power devices for future VRM

In this paper, a fully depleted LDD MOSFET built on silicon-on-oxide is proposed as a candidate device for future voltage regulator modules (VRM), which are dedicated DC/DC converters to power advanced microprocessors, and which are expected to work at multi-megahertz frequencies.