Po-Cheng Huang

Defect reduction with CMP pad dressing optimization

CMP is regarded as a process to remove material from wafer surface. And lots of mixture will be created from polishing interface. Consumables, such like pad, retainer ring, dresser and membrane will be consumed during polishing. Furthermore, abrasive, slurry chemicals and wafer surface material will have some specific interaction through well designed chemistry, which produced lots of by-products. These un-expected pollutants from consumable consumed and chemical reactions during polishing will generate defects on wafer surface, such like scratch, pits or others. This study introduces an advanced opinion to ease defect generated. We found pad dressing parameter is a highly correlation factor to post CMP defects. Over dressing condition will shorten pad life time and also create more particles in the polishing interface to cause defects on the wafer. Under dressing condition will get an unstable removal rate and uniformity through pad life time. We had found out a sweet spot for defects reductions with BSL (baseline) RR (removal rate) and uniformity retained with dressing recipe optimized.

The L28 STI CMP Dummy Pattern Study on Topography for Advanced Fixed Abrasive and High Selective Slurry

Since the sub-0.25 μm technology node, the shallow trench isolation (STI) was the process of choice to replace local oxidation of silicon (LOCOS) for the transistors of complimentary metal oxide semiconductor (CMOS) devices [1, 2]. The STI CMP performance was major determined by the uniformity of STI step height which was characterized by the ranges of within-die (WID) and within-wafer (WIW) thickness for both silicon nitride and trench oxide surface of isolation area [3]. Currently, for 28nm generation, two advanced approaches for STI CMP were high selective slurry (HSS) and fixed abrasive (FA) CMP. For these two approaches, the design and layout of dummy were important to overcome the effect of various pattern densities and feature sizes. For this reason, this research studied and compared the effect of dummy on the two different STI CMP processes and found a better way to meet the STI step height range control for 28 nm node and beyond. In this research, L28 logic pattern wafers with two different STI test keys were prepared and filled with subatmospheric chemical vapor deposition (SACVD) dielectric oxide film. Both HSS and FA STI CMP were executed for the comparison. Specific testkey sets were designed for the dummy effect study. Every testkey set have different pattern density (PD) varied from 10% to 90%. 5 testkey sets were surrounded with 5 various dummies, as showed in Table 1, independently. This research focused on the effect of dummy type for HSS and FA STI CMP. Figure 1 and 2 show the dummy effect on nitride thickness of test keys across different pattern density after HSS and FA CMP process, respectively. The pattern density of dummy shows an important effect on FA CMP. The dummy 1 which has the lowest pattern density in theses five dummies shows the worst non-uniformity of nitride thickness, which decreases as pattern density of test key lower than 70 %, after FA CMP process. On the contrary, the HSS CMP shows weak dependence on the pattern density of dummy. This result shows HSS CMP is relative insensitive to the PD of both dummy and test pattern. It is preferred for STI CMP process. On the other hand, for FA CMP, choosing proper dummy pattern is important to sustain the better non-uniformity of nitride thickness across wide PD range. In addition, this research also studied the dummy effect on trench oxide dishing, as shown in Figure 3. For HSS CMP, dishing amount is not sensitive to dummy pattern through it is higher than FA CMP process no matter the dummy type is. FA CMP process performs less dishing extent than HSS CMP process, especially in Dummy 4 and Dummy 5. It means that dummy with high pattern density and small spacing benefits to dishing performance at FA CMP. The result shows dummy layout is important for STICMP process. In this research, the dummy with higher pattern density shows better performance at nitride thickness uniformity and trench oxide dishing. Nevertheless, the CMP process is the most important factor for STICMP. The HSS CMP process has better performance at nitride thickness uniformity and is not affected by the layout of dummy.

The Amorphous-Si CMP process improvement for L14 nm FinFET technology node

Multiple gate field-effect transistors (MuGFET) are generally used in modern time semiconductor field due to better transistor current flow. However in the last advanced generation, MuGFET has transferred to Fin Field Effect Transistor (FinFET) structure with 3 dimensional (3-D) geometry to enable the minimize off-state leakage currents, high transistor current flow and quick switch...etc. advantages. But 3D structure will limit the depth of focus (DOF) of lithography. Chemical Mechanical polishing (CMP) planarization process has become more and more important to improve this issue in FinFET production. At L14 node CMP processes, a new Amorphous Si (A-Si) CMP process is introduced to reduce the roughness after the Amorphous Silicon deposition of gate. In this study, a robust ASICMP process with better A-Si polishing profile (range control), lower defectivity and better thickness control has been evaluated to meet the ASICMP process criteria at 14nm node. Optimizing the process control algorithm and down force condition for each polishing zone could improve process stable and range control. Fine tune full-vision spectrum can obvious enhance thickness control accurately.

High-k metal gate poly opening polish at 28nm technology polish rate and selective study

A robust poly opening polish (POP) CMP for replacement metal gate (RMG) application has been developed to meet the criteria of High-k metal gate (HKMG) devices at 28nm technology node. From the previous performance of POP CMP, the uniformity and loading was an important factor of product with HKMG. The polish rate and selective of platen 2, which were key physical characters, was taken to study by recipe and film type tuning. As the results, the platen and head rotate speed (rpm) can influence the selective of SiN and oxide remove rate. In addition, the SiN remove rate was been changed by different slurry shelf life.