Po-Sheng Shih

A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition

We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFTs). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) oxide performed at 23/spl deg/C. Devices fabricated with the new process exhibit a lower leakage current and a better ON/OFF current ratio than non-LDD control devices. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be quite promising for future high-performance poly-Si TFT fabrication.

Polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain

We have fabricated a polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain (SiGe-RSD TFT). The SiGe-RSD regions were grown selectively by ultrahigh vacuum chemical vapor deposition at 550 °C. It was observed that, with SiH4 and GeH4 gas flow rates of 5 and 2 sccm, respectively, the poly-SiGe could be selectively grown up to 100 nm for source/drain regions. The resultant transistor structure features an ultrathin active channel region (20 nm) and a self-aligned thick source/drain region (120 nm), which is ideally suited for optimum performance. The significant improvements in electrical characteristics, such as higher turn-on current, lower leakage current, and higher drain breakdown voltage have been observed in the SiGe-RSD TFT, compared to the conventional TFT counterpart. These results indicate that TFTs with SiGe raised source/drain structure would be highly promising for ultrathin TFTs applications.

Application of high temperature deposited aluminum gate electrode to the fabrication of a-SI:H TFT

Aluminum is a good candidate for low resistivity metal used on TFT-LCD panels as the gate electrode of a-Si:H TFTs. The characteristics of a-Si:H TFTs device are strongly dependent on the morphology of the aluminum film. However, the thermal and mechanical stability of aluminum are inferior. In this work, hot aluminum was firstly used as the gate electrode of a-Si:H TFTs. Effects of aluminum deposition temperature on the surface roughness were investigated. The fraction of Al(111) texture increases with increasing deposition temperature. The surface roughness due to hillock formation decreases with increasing deposition temperature of aluminum films. Therefore, increasing the deposition temperature of aluminum films can suppress hillock formation. The field effect mobility of a-Si:H TFTs increases with the deposition temperature of aluminum gate. The subthreshold swing of a-Si:H TFTs decreases with the deposition temperature of aluminum gate.

Interfacial reactions of Pd/Si0.76Ge0.24 by pulsed KrF laser annealing

The interfacial reactions of Pd/Si0.76Ge0.24 were studied by pulsed KrF laser annealing as a function of energy density and pulse number. At an energy density of 0.1–0.4 J/cm2, a continuous germanosilicide layer composed of a low-temperature phase, Pd2(Si1−xGex), and a high-temperature phase, Pd(Si1−xGex), was formed. In contrast to vacuum annealing, Ge segregation out of the germanosilicide layer and the strain relaxation of the residual Si0.76Ge0.24 film could be effectively suppressed by pulsed KrF laser annealing at 0.1 J/cm2. Multiple pulse annealing at 0.1 J/cm2 could further homogenize the Pd concentration of the germanosilicide layer and promote the growth of Pd(Si1−xGex). Concurrently, the smoothness of the germanosilicide layer was substantially improved in comparison with those grown by vacuum annealing at temperatures above 200 °C. The studies also revealed that for multiple pulse annealing at 0.1 J/cm2 with a low repetition rate, 1 Hz, the evolution of phase formation and Pd diffusion could b...

Annealing effects on the interfacial reactions of Ni on Si0.76Ge0.24 and Si1−x−yGexCy

Interfacial reactions of Ni/Si0.76Ge0.24 and Ni/Si1−x−yGexCy by vacuum annealing and pulsed KrF laser annealing were studied. Upon annealing at a temperature of 200–600 °C Ge segregation occurred with the extent becoming more severe at higher temperatures. The temperatures at which phase transformation and the agglomeration structure occurred were higher for Ni/Si1−x−yGexCy than for Ni/Si0.76Ge0.24. Upon pulsed KrF laser annealing the agglomeration structure was considerably improved, however, the retardation of phase transformation in the Ni/Si1−x−yGexCy system still occurred. C accumulation around the original amorphous/crystal interface formed by C+ implantation played a significant effect on delaying the phase transformation. For the Ni/Si0.76Ge0.24 and Ni/Si1−x−yGexCy samples annealed at 0.2 J/cm2 for 20 and 30 pulses, respectively, smooth Ni(Si0.76Ge0.24)2 and Ni(Si1−x−yGexCy)2 films could be grown, meanwhile Ge segregation and strain relaxation of the unreacted Si0.76Ge0.24 films were effectively s...

Analysis of Narrow Width Effects in Polycrystalline Silicon Thin Film Transistors

In this study, narrow width effects of polycrystalline silicon thin film transistors (poly-Si TFTs) are investigated. With reducing channel width, TFT characteristics such as mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow width effects, a physically-based model is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found that the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area.

A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain

With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.

Interfacial reactions of Ni/Si0.76Ge0.24 and Ni/Si1−x−yGexCy by vacuum annealing and pulsed KrF laser annealing

Abstract Interfacial reactions of Ni on Si 0.76 Ge 0.24 and Si 1− x − y Ge x C y films by vacuum annealing and pulsed KrF laser annealing were studied by transmission electron microscopy (TEM) in conjunction with energy dispersive spectrometry (EDS) and X-ray diffraction (XRD). For the Ni/Si 0.76 Ge 0.24 and Ni/Si 1− x − y Ge x C y films annealed at a temperature of 200–600°C Ge segregation and agglomeration occurred at an extent becoming more severe at higher temperatures. Upon pulsed KrF laser annealing the agglomeration structure was improved. The retardation of phase transformation in the Ni/Si 1− x − y Ge x C y system was observed upon either vacuum annealing or pulsed laser annealing. Multiple-pulse annealing is an effective method to fabricate smooth Ni(Si 0.76 Ge 0.24 ) 2 and Ni(Si 1− x − y Ge x C y ) 2 films without inducing Ge segregation to the remaining substrates and strain relaxation.

The effects of microcrystalline silicon film structure on low-high-low band-gap thin film transistor

The effects of hydrogenated microcrystalline silicon (μc-Si:H) film with various crystalline factors on thin-film transistors (TFTs) with low-high-low band gap structure are studied. Compared to hydrogenated amorphous silicon (a-Si:H) TFT with conventional inverted-stagger structure, the device with μc-Si:H film of high crystalline factor in the active channel depicts improved interfacial active layer near the gate insulator interface as well as the later-grown bulk active layer, resulting in improved device parameters including field effect mobility, threshold voltage, subthreshold swing and ON-current. While a-Si:H film of low crystalline factor and high-band-gap is proposed for the source and drain offset regions in the new device to prevent the band-to-band tunneling, thus alleviates the high OFF-current inherent in conventional μc-Si:H thin-film transistors, resulting in an improved ON/OFF current ratio.

Room temperature oxidation of Cu/Si0.76Ge0.24 annealed at 200 to 300°C

The Cu3Si-catalyzed oxidation behavior of Cu/Si0.76Ge0.24 after annealing at a temperature of 200–300°C was studied using transmission electron microscopy (TEM). For the Cu/Si0.76Ge0.24 samples annealed at 200°C and followed by exposure in air for 1–4 weeks an SiO2 layer embedded with precipitates containing Cu, Ge, Si, and O was formed on the surface of the Cu3(Si1−xGex) film. During exposure the Cu atoms released from Cu3(Si1−xGex) by oxidation diffused down to the residual Si0.76Ge0.24 film and subsequently the Si substrate to form new Cu3(Si1−xGex) and Cu3Si, respectively. After exposure for 5–6 weeks not only the oxidation of the surface layer became severe but also the growth of the buried SiO2 layer was initiated at the Cu3(Si1−x)/Cu3Si interface. Concurrently, the Cu3Si-catalyzed oxidation of Si by inward movement of the SiO2/Si interface was also observed. As compared with the annealed Cu/Si samples the presence of Ge significantly lowered the oxidation rate of the annealed Cu/Si0.76Ge0.24 samples. Higher temperature annealing promoted the oxidation rate because of Ge segregation out of the Cu3(Si1−xGex) layer and the formation of a larger fraction of the Cu3(Si1−xGex)/Cu3Si interface where the buried SiO2 layer was initially formed.