Wenqi Zhang

Effect of thermal annealing on TSV Cu protrusion and local stress

Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical behavior of the TSV having a diameter of 20 μm and a depth of 120 μm under different annealing temperatures. The measured protrusion increases with annealing temperature below 400°C, and then decreases when being further annealed. The maximum measured silicon stress as a function of annealing temperature has shown similar trend to the protrusion. The pre-annealing has limited effect on protrusion, but is helpful to reduce the silicon stress.

A cost effective method for TSV backside reveal

Through Silicon Via (TSV) can be used to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. Via Reveal-a kind of wafer back side process moduleplays an important role in the successful implementation of TSV. In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etching process. So in this paper, we will focus on the TSV reveal unit process. Firstly, we will briefly review TSV integration technology; Then a set of experiments is described which were used to select etch parameters to achieve the desired etching rate, selectivity and profile. Lastly we will show the results of TSV reveal using wet etching process. The proper composition of the HNO3/HF/CH3COOH(HNA) solutions, etching parameter, and TEOS deposited by proper temperature provide the necessary process control and etching selectivity that enable the use of higher throughput wet etch for TSV back etch.

Effect of annealing after copper plating on the pumping behavior of through silicon vias

Though Silicon Vias(TSVs) are regarded as a key technology to achieve three dimensional(3D) integrated circuit(IC) functionality. Annealing a silicon device with TSVs may cause high stress and cause TSV protrusion because of high Coefficient of Thermal Expansion(CTE) between silicon substrate and TSVs. The TSV wafers could be annealed right after copper plating process, or after chemical mechanical polish (CMP) process, or both. In this paper, we report our research progress on the effect of annealing right after copper plating on the pumping behavior at different temperatures. Then the copper overburden is removed by CMP. The TSV wafers are tested at different temperatures for 30 minutes, 250°C, 300°C, 350°C, 400°C, 450°C, respectively. The pumping is measured by optical profiler, BRUKER Contour GT-X3. The finite element analysis method, ANSYS, is used to model and simulate the copper pumping at different temperatures. The pumping results with annealing at different temperatures are compared with those without annealing. It reveals that the pumping with annealing is larger than that without annealing. This is possibly due to higher level of stress release and microstructure evolution.

Robust and Low Cost TSV Backside Reveal for 2.5D Multi-Die Integration

TSV backside reveal is one of the key process modules for enabling 2.5D integration. This paper presents a robust and low cost solution for TSV backside reveal. 300mm wafers with a TSV size of 10μm×100μm are used to evaluate the proposed backside reveal solution. A high selective wet etching process with an etch rate of about 15 μm/min is used to replace conventional Si dry etching step for Si recess etch. A low temperature cured polyimide layer is used for the backside passivation and an innovative exposure treatment is employed to expose the back tip of the TSVs. After silicon oxide dry etching, the TSV metal is revealed for backside interconnection. This process can avoid Si dry etching, plasma deposition and chemical mechanical polishing (CMP) processes and hence the overall cost is significantly reduced. Furthermore, the process margin for TTV control is also relaxed, which leads to a robust process result. Electrical test results for TSV kelvin and TSV daisy chain show a high process yield and a low contact resistance between the TSV back tip and backside RDL layer. Finally, 2.5D multi-die integration is demonstrated based on the proposed process.

One-Step Dipping Method for Covalently Grafting Polymer Films onto a Si Surface from Aqueous Media

A facile and one-pot dipping method was proposed in this article for the first time to prepare vinylic polymer films on a silicon (Si) surface. This novel process was conducted in acidic aqueous media containing 4-nitrobenzene diazonium (NBD) tetrafluoroborate, hydrofluoric acid (HF), and vinylic monomers at room temperature in the open air and without any apparatus requirement. The formation of the polyvinyl film was confirmed by corroborating evidence from ellipsometry, Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectroscopy (XPS), and atomic force microscope (AFM) analysis. The results revealed that both polymers of poorly water soluble methyl methacrylate (MMA) and water-soluble acrylic acid (AA) monomers were covalently grafted onto the Si surface via this simple process. The polyvinyl film was composed of polynitrophenyl (PNP) and polyvinyl, where PNP was doped into polyvinyl chains throughout the entire film. From a mechanistic point of view, the simple dipping method took advantage of the ability of the NBD cation to be spontaneously reduced at the Si surface at open circuit potential, providing aryl radicals. These radicals can be covalently bonded to the Si surface to form the PNP primer layer. Although the PNP sublayer was thinner and difficult to detect, it was necessary to graft polyvinyl chains. Furthermore, the aryl radicals were used to initiate the polymerization of vinylic monomers. The radical-terminated polyvinyl chains formed in the solution were then added to the aromatic rings of the primer layer to form the expected polyvinyl film.

Influence of thermal annealing on the deformation of Cu-filled TSV

Through silicon via (TSV) is regarded as one of the most advanced packaging technologies, however, many serious reliability issues need to be paid more concerns. The Cu pumping effect is one of the most crucial reliability problems. Due to different coefficient of thermal expansion for different packaging materials, Cu-TSV can deform and damage the wiring redistribution layers and degrade the reliability of the package as a whole during normal processing. Therefore, this work focuses on the influence which different thermal annealing processes have on Cu pumping in Cu-filled TSVs. Cu TSVs having 20μm in diameter and 120μm in depth were fabricated on 200 mm wafers by etching, insulation layer deposition, barrier layer deposition, seed layer deposition and Cu plating in sequence. Then the wafer surface was polished to remove the excessive Cu. Two anneal approaches were designed to investigate Cu TSV pumping. One was CMP first before annealing, and the other was annealing before CMP and followed by the 2nd annealing. Anneal tests were done in a nitrogen environment to protect Cu from oxidation. The annealing temperatures were set at 300°C and 400°C with a dwell time of 40min. The degree of pumping was evaluated by measuring the height and volume profiles before and after annealing by using a white light interferometer. Results show that the Cu TSV increased by 0.105μm and 0.168μm in height and 90.443μm3 and 93.993μm3 in volume at 300°C and 400°C with CMP first approach. However, the Cu TSV increased by only 0.066μm and 0.075μm and 30.797μm3 and 10.077μm3 in volume at 300°C and 400°C with anneal first approach. It can be concluded that the Cu pumping effect may be restrained by anneal first approach.

Si dry etching for TSV formation and backside reveal

In 3D IC packaging, through silicon via (TSV) technology is being considered as a promising technology, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, dry etch process plays an important role in TSV fabrication. TSVs with diameters ranging from one hundred to ten micrometers are mainly fabricated by deep reactive ion etching (DRIE) technology. Bosch process is used for DRIE process for producing high-aspect ratio TSVs and non-Bosch process is used for TSV reveal process. In Bosch process, the primary steps are silicon isotropic etching and wall passivation in sequential cycles. SF6 is widely used as the main etching gas for the high density of F+ radicals; C4F8 is used in wall passivation as it polymerizes to deposits on walls to form an etch barrier that is sufficiently impervious to side scattered F+ ions but not to direct ions at the bottom of the via. Wall scalloping occurs primarily near the top of the via where scattered ions have wide trajectories and less at greater depths where ion trajectories are more restricted. After completion of the via-middle TSV integration and front-side wafer processing, the wafer is temporarily bonded onto a carrier wafer which could be glass or silicon. Then Si from the backside of the wafer was removed to make contact with the bottom of the TSVs by a mechanical grind followed by a reveal etch, which is a key step for the successful implementation of TSV. The via reveal was required to maintain acceptably low total thickness variation (TTV) to allow subsequent stacking steps.

Effects of Sn grain size on intermetallic compounds formation in 5 µm diameter Cu/Sn pillar bumps

Uniform 5xa0µm diameter Cu/Sn micro-bump array has been fabricated by multilayer electrodeposition, and the effect of Sn grain orientation and size on Cu6Sn5 and Cu3Sn growth have been studied through FIB–SEM and electron backscatter diffraction. The solder layer in Ф5xa0µm Cu/matte Sn micro-bump we fabricated contains only four to five columnar Sn grains with no obvious preferred orientation and there is no significant difference in the growth of Cu6Sn5 in different oriented Sn grains. However, the Sn grain size has much more effect on intermetallic compound (IMC) growth. At 150xa0°C, the diffusion coefficient of Cu/bright-Sn system(~u2009200xa0nm Sn) is calculated to be 13.09u2009×u200910−17xa0m2xa0s−1, nearly three times that of Cu/matte–Sn system (2–5xa0µm Sn), about 4.51u2009×u200910−17m2xa0s−1. Also, a simple model of boundary diffusion controlled IMC growth is proposed to explore the mechanism of grain size effect. Large Sn grain size will slow down the interfacial reaction in micro-bump due to low grain boundary density and large bulk diffusion distance.

Investigation of intermetallic compound and voids growth in fine-pitch Sn–3.5Ag/Ni/Cu microbumps

Micron level Cu-pillar microbumps, which appear as the size of three-dimensional packaging shrinks down, have to introduce many unexpected reliability problems. The fast growth of intermetallic compounds (IMC) and voids tend to be a serious one. In this paper, the growth behaviors of IMC and voids were investigated in Sn–3.5Ag/Ni/Cu bumps, which were in the diameter ranging from 6 to 11xa0μm and fabricated under same reflow process. The consequence manifested that the growth rate of interfacial IMC increased from 0.448 to 0.578xa0μm/min as the bump diameter decreased from 11 to 6xa0μm and the acquired IMC could be divided into two layers: the (Cu, Ni)6Sn5 layer and Ni3Sn4 layer. As a result of the migration of Ni atoms, many voids were left in the interface between (Cu, Ni)6Sn5 and Ni3Sn4. In the edge of Cu pillar, side wall wetting reaction was detected, which was confirmed by the formation of voids and (Cu, Ni)6Sn5 phase. Further, as the bump diameter decreased, the side wall wetting reaction aggravated, which partly contributed to the acceleration of IMC growth.

Competitive adsorption between suppressor and accelerator in copper methanesulfonic acid bath for electrodeposition

The rapid development of three dimensional packaging makes it necessary to develop smaller and more reliable microbumps. In the electrodeposition process of bump cylinder, the filling quality is largely determined by the combination of additives. In this work, the effect and competitive adsorption between suppressor polyethylene glycol (PEG) and accelerator Bis-(3-sodiumsulfopropyl disulfide) (SPS) were investigated in copper methanesulfonic acid (MSA) plating bath. The results indicated that suppressor inhibited the Cu+/Cu reduction process in copper deposition by forming PEG-Cl−-Cué passivation film on the electrode surface. And the inhibiting effect was found to reach saturation when suppressor concentration reached above 9 mg/L, due to the coverage limitation of suppressor absorption. When accelerator was added into plating bath with PEG, SPS was supposed to disrupt or displace the adsorbed PEG and to form a bridge (RS-Cu2+-Cl−) with the electrode metal, which speed up the charge-transfer process. Thus the electrochemical process was converted to be diffusion controlled.