G. Van der Plas

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Performance degradation of an LC-tank VCO by impact of digital switching noise

In mixed-signal designs, digital switching noise is an important limitation for the analog and RF performance. This paper reports a thorough experimental and analytical study of the impact of digital switching noise on a 3.5 GHz LC-tank voltage controlled oscillator (VCO) in 0.18 /spl mu/m CMOS. Frequency modulation is recognized as the dominating mechanism behind the impact of digital switching noise in the investigated frequency range (DC to 15 MHz). The dominating coupling path, from the source of noise to the VCO, in this frequency range is via the non-ideal metal ground lines.

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance

The paper reports a novel simulation methodology for the analysis and prediction of substrate noise impact on analog/RF circuits taking into account the role of the parasitic resistance of the on-chip interconnect in the impact mechanism. This methodology allows investigation of the role of the separate devices (also parasitic devices) in the analog/RF circuit in the overall impact. In this way, it is revealed which devices have to be taken care of (shielding, topology change) to protect the circuit against substrate noise. The developed methodology is used to analyze the impact of substrate noise on a 3 GHz LC-tank voltage controlled oscillator (VCO) designed in a high-ohmic 0.18 /spl mu/m 1 PM6 CMOS technology. For this VCO (in the investigated frequency range from DC to 15 MHz) impact is mainly caused by resistive coupling of noise from the substrate to the non-ideal on-chip ground interconnect, resulting in analog ground bounce and frequency modulation. Hence, the presented test-case reveals the important role of the on-chip interconnect in the phenomenon of substrate noise impact.

Study of the different coupling mechanisms between a 4 GHz PPA and a 5–7 GHz LC-VCO

The coupling of the transmitted RF signal of the power amplifier (PA) into the sensitive voltage controlled oscillator (VCO) of a transceiver can cause failure of the RFIC. It is not obvious for the designer to identify which coupling mechanism can be held responsible for the degradation of the VCO. Thus it remains an open problem to decide which appropriate countermeasure should be taken. Different experiments are carried out on a 0.13 mum CMOS 4 GHz PPA and a 5-7 GHz LC-VCO to gain insight in the different coupling mechanisms.

Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs

Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners (“donut TSVs”) and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.

Modeling the effect of charges in the back side passivation layer on through silicon via (TSV) capacitance after wafer thinning

Evaluating the importance of electromagnetic (EM) coupling from through silicon vias (TSVs) has become crucial to the design of three-dimensional integrated circuits (3D-ICs). One of the most important parasitic contributions to signal propagation in 3D-ICs is the TSV capacitance. It is both frequency and bias dependent since a TSV is a metal-oxide-semiconductor (MOS) structure. In this work, anomalous TSV capacitance behavior after wafer thinning is reported and investigated by combining measurements and finite element (FEM) semiconductor simulations. Excellent agreement between models and experimental data confirms the origin of the anomalous TSV capacitance behavior: the presence of fixed charges in the back side (BS) passivation layer of the TSV after wafer thinning. In addition, a BS inversion layer can act as a conductive channel between neighboring vias, increasing the capacitive coupling between TSVs. Calibrated equivalent circuit models of the TSV in contact with a BS inversion layer are proposed for the first time in the context of 3D integration and validated.

Advanced nonlinearity analysis of a 6 GHz wideband receiver

CMOS receivers need to comply to stringent linearity specifications. Due to the high complexity of those receivers, it is not obvious for the designer to identify the nonlinear behavior. To gain insight in the nonlinear behavior we use an advanced multisine method that pinpoints the dominant nonlinear device in the receiver. This is demonstrated on a 90 nm CMOS wideband receiver where the different distortion mechanisms are revealed. Insights in those distortion mechanisms can be used to reduce the nonlinear behavior of the overall receiver. The receivers output distortion, that is predicted with this method, is successfully verified with measurements.

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs

Energy-recovering schemes have been proposed in the literature as an alternative approach to low-power design, while their performance has been demonstrated to be extremely promising when driving large capacitive loads, such as clock distribution networks [1]. This work investigates the potential of the energy-recovering methodology for improving the energy efficiency of through-silicon via (TSV) interconnects in 3D ICs.

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.

Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning

This paper investigates the influence of TSV noise coupling on nearby devices based on an extended 3D TSV circuit model. This model not only takes into account the complex RF field distributions in bulk Si, but also incorporates the anomalous TSV capacitance inversion behavior, which has been found to occur due to the presence of fixed charges in the backside passivation layer after wafer thinning. The extended 3D TSV circuit model is validated by the excellent agreement between the simulation results and experimental data. It demonstrates that the inversion behavior of the TSV capacitance increases the noise coupling to adjacent devices mainly in the low frequency range. Furthermore, we show that noise mitigation techniques can be easily implemented in this 3D circuit model to predict the extent of noise coupling alleviation.