Dake Wu

A 0.4-V Low Noise Amplifier Using Forward Body Bias Technology for 5 GHz Application

A fully integrated low noise amplifier (LNA) suitable for ultra low voltage and ultra low power applications is proposed and demonstrated in 0.13 mum CMOS technology. In order to meet the requirement of ultra low voltage applications, a two-stage common-source configuration is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed LNA can operate at 0.4 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The experimental results show that the proposed LNA has a 10.3 dB power gain and a 5.3 dB noise figure, while consuming only 1.03 mW dc power with an ultra low supply voltage of 0.4 V.

Unipolar Resistive Switch Based on Silicon Monoxide Realized by CMOS Technology

In this letter, a reliable nonvolatile resistive switching device based on silicon monoxide (SiO) is demonstrated. The device was fabricated with a low-temperature process that can be compatible with a CMOS back-end process and attractive for 3-D memory integration. The fabricated Cu/SiO/W device was found to have a repeatable unipolar resistive switching behavior. The results show excellent on/off resistance ratio (over 104) and good retention performance. The switching mechanism of the device is analyzed by experimental data and probably can be attributed to the behaviors of copper ions in the bulk of SiO under different voltages.

A Novel RF LDMOS Fabricated With Standard Foundry Technology

In this letter, a novel LDMOS structure is proposed and experimentally demonstrated with standard foundry CMOS technology. The device features both an inserted oxide layer in the drift region as the ldquoelectric field line absorberrdquo and a high-doped region introduced for action of the RESURF-like structure. The RESURF-Dielectric-region-Inserted LDMOS device with breakdown voltage of about 15 V and peak cutoff frequency of 18 GHz is obtained. The proposed device also exhibits good reliability behavior under high-voltage stressing. The new device is very promising for integrated power amplifier circuit design with the standard CMOS process.

Impact of proton-radiation-induced spacer damage on the dc characteristics degradation in deep-submicron metal-oxide-semiconductor field effect transistors

The dc characteristics degradation of 0.18 μm metal-oxide-semiconductor field effect transistors (MOSFETs) after 10 MeV proton irradiation is comprehensively investigated in this paper. The measured results show that the off-state drain current is increased in N-channel MOSFETs, which is due to the turn on of the parasitic transistors induced by the shallow trench isolation regions. While in P-channel MOSFETs, the threshold voltage increase (absolute value), the transconductance degradation, and the saturation drain current decrease are observed. From the analysis, it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the isolation region. The origin of the observed changes may be mainly due to the damage in the spacer oxides of the transistors. In order to verify the assumption, the leakage current passing through the spacer between the gate and the drain is measured before and after irradiation with floated source/substrate and grounded drain. We find that the leakage current is two to three times larger after irradiation. Finally, in order to confirm the extrapolation, 2-dimension (2D) simulation has been performed with Synopsys TCAD (technical computer-aided design) Sentaurus Device Simulation tools (ISE 10.0). The behavior of the simulated charges trapped in the spacers is qualitatively consistent with the experimental results.The dc characteristics degradation of 0.18 μm metal-oxide-semiconductor field effect transistors (MOSFETs) after 10 MeV proton irradiation is comprehensively investigated in this paper. The measured results show that the off-state drain current is increased in N-channel MOSFETs, which is due to the turn on of the parasitic transistors induced by the shallow trench isolation regions. While in P-channel MOSFETs, the threshold voltage increase (absolute value), the transconductance degradation, and the saturation drain current decrease are observed. From the analysis, it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the isolation region. The origin of the observed changes may be mainly due to the damage in the spacer oxides of the transistors. In order to verify the assumption, the leakage current passing through the spacer between the gate and the drain is measured before and after irradiation with floated source/substrate and grounded drain. We find that the leakage cur...

A Low-Voltage and Low-Power CMOS LNA Using Forward-Body-Bias NMOS at 5GHz

A fully integrated LNA suitable for ultra-low-voltage and ultra-low-power applications is designed in 0.13 mum CMOS technology. A two-stage common-source configuration and forward-body-bias MOSFET are employed to reduce the supply voltage. The proposed LNA exhibits 14.3dB power gain and 2.93dB noise figure at 5GHz while consuming only 0.64mW DC power at the ultra-low supply voltage of 0.4V

Scaling capability improvement of silicon-on-void (SOV) MOSFET

In this paper, the scaling capability improvement of silicon-on-void (SOV) MOSFET is comprehensively investigated. The results show that SOV MOSFET shows a significant improvement in the suppression of the short-channel effects (SCE) caused by the potential coupling between the source and drain through the buried layer. In addition, the parasitic capacitance between the source/drain and the substrate can be greatly decreased. The minimal channel length of SOV MOSFET is reduced by 27% compared with ultra-thin-body (UTB) SOI MOSFET. Most of all, the limitation of silicon film thickness of SOV MOSFET can be relaxed to about 50%, in comparison with SOI MOSFET. SOV MOSFET can alleviate the critical problem and further improve the immunity of SCE of UTB SOI MOSFET in the nanoscale regime. SOV MOSFET will be a good choice of device structure to put off the eventual limit in scaling down.

Novel vertical channel double gate structures for high density and low power flash memory applications

The flash memory technology meets physical and technical obstacles in further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell benefits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications.

Performance Improvement of Capacitorless Dynamic Random Access Memory Cell with Band-Gap Engineered Source and Drain

A novel band-gap engineered source and drain floating body cell (BESD-FBC) for capacitorless dynamic random access memory (DRAM) Cell is proposed and investigated for the first time. The energy band offset with silicon–carbon source and drain can help to form a deeper potential well in the body region, which can effectively store more holes. Compared with normal FBC, BESD-FBC can obtain larger sensing margin and longer retention time due to more stored holes and small hole leakage current. These improvements show that the proposed BESD-FBC has great potentials for future high density capacitorless DRAM application.

The parasitic effects induced by the contact in RRAM with MIM structure

This paper has reported a programmable switch composed of copper-doped-SiO2 sandwiched between Cu top electrode and inert W bottom electrode. Reproducible rectifying-like I-V performance was found in the device with top electrode (TE), while with regard to the cell without TE, no rectifying-like I-V characterization was observed. This rectifying-like I-V curve is properly caused by electrode contact. To further prove the effect of TE, RON retention behavior of the device with TE and without TE were investigated. The testing results clearly showed that the RON retention property of device with TE was worse than that without TE. We propose a model for the interface between top electrode and copper-doped-SiO2 to interpret this rectifying-like performance, which indicates that interface rectifying-like effect emerges when on-resistance is comparable with the resistance of diode-like junction between metal contact and resistive-material. The results suggest that optimizing interface condition or adjusting resistive material with large on-resistance is essential for robust MIM RRAM design.

Performance improvement of flash memory with a novel quasi-SOI structure

A novel quasi-silicon-on-insulator (quasi-SOI) flash memory cell is proposed for the first time. By utilizing quasi-SOI structure, program/erase (P/E) performance improvement is achieved due to the enhancement of electric field in the injection region, compared with conventional cell structure. Moreover, the off-state current at large drain bias is greatly reduced by 2 orders of magnitude with the help of the L-shaped dielectric layer, indicating better program-failure immunity and lower unexpected power consumption. With punch-through effect alleviated, the novel flash cells have better scalability. Through the results and analysis, the proposed flash cell can be a potential candidate for NOR-type applications.