Pradeep Kumar Nalla

GLA: gate-level abstraction revisited

Verification benefits from removing logic that is not relevant for a proof. Techniques for doing this are known as localization abstraction. Abstraction is often performed by selecting a subset of gates to be included in the abstracted model; the signals feeding into this subset become unconstrained cut-points. In this paper, we propose several improvements to substantially increase the scalability of automated abstraction. In particular, we show how a better integration between the BMC engine and the SAT solver is achieved, resulting in a new hybrid abstraction engine, that is faster and uses less memory. This engine speeds up computation by constant propagation and circuit-based structural hashing while collecting UNSAT cores for the intermediate proofs in terms of a subset of the original variables. Experimental results show improvements in the abstraction depth and size.

FVCAG: A framework for formal verification driven power modeling and verification

Generation of accurate IP power models requires determination of correct simulation conditions for the different input pins of the IP. Determining such a set of inputs for individual IP blocks in a design is expensive in cost and time, and is also highly error prone. Additionally, it is desirable to identify IP instances in a design, where these simulation conditions are not met. These are relevant problems in the context of modern day microprocessor designs, which are designed using a very large number of IPs, either developed in-house or sourced from external vendors. In this paper, we examine these problems in an industrial context and introduce FVCAG, a framework for enabling efficient and accurate power modelling. FVCAG enables a more thorough IP power modelling than that can be accomplished using current state of the art techniques. Experimental evaluation of the proposed framework on the standard cell library and macros used in the design of an industry class high performance microprocessor design demonstrates the accuracy and efficiency of proposed framework.

The art of semi-formal bug hunting

Verification is a critical task in the development of correct computing systems. Simulation remains the predominantly used technique to identify design flaws, due to its scalability. However, simulation intrinsically suffers from low functional coverage, hence often fails to identify all design flaws. Formal verification (FV) is a promising approach to overcome the coverage limitations of simulation, due to its exhaustiveness - which enables it to identify intricate design flaws too complex to practically find using simulation. However, automated FV techniques have scalability drawbacks that limit the size of design components that can be formally verified. One of the key strengths of FV techniques is their use of symbolic reasoning, to efficiently explore a huge number of individual scenarios that would be intractable using simulation. When used in an incomplete manner, the scalability challenges of these algorithms are lessened, enabling efficient and relatively scalable semi-formal bug hunting. Nonetheless, to yield a robust industrial-strength solution, the individual components of such a system - many being heuristic - must be highly tuned, and integrated and orchestrated in an intricate manner. In this paper, we overview the various components useful in a scalable semi-formal search framework, introducing several novel powerful techniques and providing experimental data to illustrate the strengths, weaknesses, and complementary nature of the various techniques.