Hari Balachandran

K longest paths per gate (KLPG) test generation for scan-based sequential circuits

To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are inefficient in automatically identifying the longest testable paths due to the high computational complexity. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on ISCAS89 benchmark circuits and industrial designs. Experiments show that testing transition faults through the longest paths can be done in reasonable test set size.

Clustering based techniques for I/sub DDQ/ testing

A new technique for evaluating I/sub DDQ/ data using a clustering based approach is presented. While prevailing I/sub DDQ/ test techniques rely on a fixed threshold or the current signature of an IC, the proposed technique relies on abnormalities of the I/sub DDQ/ distribution of a device with respect to other devices in the test set. Results of applying this technique to data collected on a high volume graphics chip are described. Results are also compared to the conventional single threshold approach, and benefits of the new technique are presented.

Correlation of logical failures to a suspect process step

Traditional yield enhancement efforts have long relied on memory bitmapping techniques. With the industry marching toward system-on-a-chip technology, the importance of logic products has increased exponentially. This necessitates the development of innovative techniques to perform logic yield enhancement. In this paper the authors present a novel technique that can be used to perform logic yield enhancement. The paper concentrates on logic bitmapping at Texas Instruments. Results obtained from a few production samples of a graphics processor are also presented.

Facilitating rapid first silicon debug

Semiconductor manufacturers aim to deliver products to market within a short span of time in order to gain market share. There are several facets of introducing a product to market - design, manufacturing, first silicon debug, and ramp to volume. Of these, first silicon debug time contributes significantly towards reduced product cycle time if it can be kept short. In this paper, we discuss the infrastructure, design tools, test tools and debug tools required to achieve successful first silicon debug. We describe a production device that employs these infrastructure requirements, thereby demonstrating the advantages of following the guidelines. The paper also highlight the ill effects of not adhering to the guidelines.

Clustering based evaluation of I/sub DDQ/ measurements: applications in testing and classification of ICs

Effectiveness of the clustering based approach in detecting devices with abnormal I/sub DDQ/ values is evaluated using data from the SEMATECH test methods experiment. The results from clustering are compared to the results obtained on actual silicon during the SEMATECH study. The differences between the results obtained in each case are analyzed. The clustering approach is also compared to two common I/sub DDQ/ test techniques, the single-threshold approach and the delta-I/sub DDQ/ approach, and the results are presented.

Computer-aided fault to defect mapping (CAFDM) for defect diagnosis

Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this work we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by injecting bridging faults into samples of a Streaming audio controller chip and comparing the predicted defect locations and layers with the actual values. The correct defect location and layer was predicted in all 9 samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results.

Clustering based identification of faulty ICs using I/sub DDQ/ tests

Technological advances in design and process have led to questions being raised about the applicability of I/sub DDQ/ testing. The main concern is the inability to differentiate between normal and faulty quiescent currents in ICs. In this paper, we propose a new methodology aimed at addressing this concern through the application of clustering techniques to identify ICs with abnormal I/sub DDQ/ values. Preliminary results of applying this technique in production test are also presented.

Defect localization using physical design and electrical test information

In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to correctly identify the defect location and layer in all 9 of the chips that had bridging faults injected via FIB. Preliminary failure analysis results on production defects are promising.

Expediting ramp-to-volume production

High levels of integration have complicated the entire IC manufacturing process. Crucial steps such as ramp to volume production and yield improvement techniques are being challenged. In this paper, a diagnostic system that has been developed and deployed into a production environment is presented. Experiments conducted demonstrating the value of the diagnostic tool and its limitations are presented.