Prasanna Sundararajan

A Self-reconfiguring Platform

A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. This platform has been implemented on Xilinx Virtex II tm and Virtex II Pro tm devices. The platform’s hardware architecture has been designed to be lightweight. Two APIs (Application Program Interface) are described which abstract the low level configuration interface. The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources. It also provides support for relocatable partial bitstreams. The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry.

CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures

This paper describes CHiMPS, a C-based accelerator compiler for hybrid CPU-FPGA computing platforms. CHiMPSpsilas goal is to facilitate FPGA programming for high-performance computing developers. It inputs generic ANSIC code and automatically generates VHDL blocks for an FPGA. The accelerator architecture is customized with multiple caches that are tuned to the application. Speedups of 2.8x to 36.9x (geometric mean 6.7x) are achieved on a variety of HPC benchmarks with minimal source code changes.

Performance and power of cache-based reconfigurable computing

Many-cache is a memory architecture that efficiently supports caching in commercially available FPGAs. It facilitates FPGA programming for high-performance computing (HPC) developers by providing them with memory performance that is greater and power consumption that is less than their current CPU platforms, but without sacrificing their familiar, C-based programming environment. Many-cache creates multiple, multi-banked caches on top of an FGPAs small, independent memories, each targeting a particular data structure or region of memory in an application and each customized for the memory operations that access it. The caches are automatically generated from C source by the CHiMPS C-to-FPGA compiler. This paper presents the analyses and optimizations of the CHiMPS compiler that construct many-cache caches. An architectural evaluation of CHiMPS-generated FPGAs demonstrates a performance advantage of 7.8x (geometric mean) over CPU-only execution of the same source code, FPGA power usage that is on average 4.1x less, and consequently performance per watt that is also greater, by a geometric mean of 21.3x.

CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures

This paper describes CHiMPS, a C-based accelerator compiler for hybrid CPU-FPGA computing platforms. CHiMPSpsilas goal is to facilitate FPGA programming for high-performance computing developers. It inputs generic ANSIC code and automatically generates VHDL blocks for an FPGA. The accelerator architecture is customized with multiple caches that are tuned to the application. Speedups of 2.8x to 36.9x (geometric mean 6.7x) are achieved on a variety of HPC benchmarks with minimal source code changes.

FPGA implementation of the ray tracing algorithm used in the XPATCH software

Ray tracing is one of the most popular and powerful image synthesis technique for creating photo-realistic images. In this research, we focus on the time critical application of ray tracing in the XPATCH software for high-resolution radar simulation and detection. Of particular interest to us is the ray/box intersection algorithm employed in the XPATCH ray tracer for achieving faster execution time. The ray/box algorithm is used to determine whether a ray hits or misses the target enclosed in a rectangular bounded volume.

XVPI : A Portable hardware/software interface for virtex

XVPI, the Xilinx Virtex Portable Interface, is a hardware / software interface and specification to assist in the design and implementation of Xilinx Virtex (tm) based systems. XVPI specifies a software accessible register to be defined in the hardware. This register contains all of the control and data signals necessary to drive the Virtex device. The software supplied with XVPI uses this register to read and write control and data signals to perform various device level functions. These functions combine to produce an Application Program Interface (API) which provides access to the Virtex device from software. The XVPI API supports all of the device level operations including partial configuration download, partial configuration readback, clock control and reset. Once the system is operational, designers may replace the software routines in the XVPI API with hardware assisted routines. This increases the system performance incrementally, without affecting the functionality. Though specified for the Virtex based system, this technique to perform the device level functions from software can be applied to any FPGA device. Additionally, XVPI is also supplied with an interface supporting Xilinxs JBits toolkit. Once XVPI is implemented, JBits and its associated applications, including the BoardScope debug tool, are fully operational on that Virtex based system.

Run-Time defect tolerance using JBits

The ability to tolerate defects in semiconductor devices has the potential for both increasing yields of devices being manufactured and making it economically feasible to manufacture even larger devices. While FPGA devices appear to be well suited to providing defect tolerance, practical application of existing research and techniques has been somewhat elusive. One barrier to acceptance is that existing defect tolerance techniques for FPGAs have tended to rely on either modifications to device architectures or modifications to design tools. We describe a software-based technique for providing defect tolerance which requires neither changes to device hardware or software tools. This approach uses the Xilinx JBits

XHWIF: a portable hardware interface for reconfigurable computing

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Reconfiguration of a programmable logic device using internal control

toolkit and operates at the core library level. Addressing defect tolerance locally using core library elements rather than taking a global approach helps provide direct support for run-time reconfiguration. Circuits may be configured and reconfigured rapidly in the presence of these defects. This rapid configuration also provides a path for practical use in more traditional manufacturing environments.

JBits: Java based interface for reconfigurable computing

As the interest in FPGA-based hardware has grown, so has the number and type of commercially available platforms. The greatest drawback to this proliferation of hardware platforms is the lack of standards. Even boards using identical hosts, FPGA devices and bus interfaces typically have widely varying software interfaces, limiting the portability of tools and applications across these platforms. Xilinxs XHWIF(tm) portable hardware interface attempts to address this problem. The XHWIF interface provides a software layer providing all necessary communication and control for generic FPGA-based hardware. This interface permits tools and applications to be run on a variety of platforms, typically without modifications or re-compilation. In addition, a remote network interface is supplied as part of XHWIF API. Applications and tools which use the XHWIF interface can also run transparently across a network without modification. This permits not only sharing of hardware resources in a networked environment, but a simple way of implementing systems which use Remote Network Reconfiguration. XHWIF API is currently provided as part of Xilinxs JBits (tm) Software Development Kit.