Scott P. McMillan

A Self-reconfiguring Platform

A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. This platform has been implemented on Xilinx Virtex II tm and Virtex II Pro tm devices. The platform’s hardware architecture has been designed to be lightweight. Two APIs (Application Program Interface) are described which abstract the low level configuration interface. The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources. It also provides support for relocatable partial bitstreams. The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry.

A Lightweight Approach for Embedded Reconfiguration of FPGAs

This paper presents a lightweight approach for embedded reconfiguration of Xilinx Virtex II/spl trade/ series FPGAs. A hardware and software infrastructure is reported that enables an FPGA to dynamically reconfigure itself under the control of a soft microprocessor core that is instantiated on the same array. The system provides a highly integrated, lightweight approach to dynamic reconfiguration for embedded systems. It combines the benefits of intelligent control, fast reconfiguration and small overhead.

A high I/O reconfigurable crossbar switch

A crossbar switch with 928 inputs and 928 outputs is presented. Switching elements are constructed using logic in the routing fabric. This approach yields a 16/spl times/ improvement in logic density compared with using conventional logic. Normally, the routing is fixed. However, in FPGAs (field programmable gate arrays), the interconnection is defined by the state of SRAM configuration cells, which are dynamically modifiable. Therefore, the switch is implemented on an FPGA using partial configuration to modify routing resources during operation. All paths are synchronously clocked at 155.5 MHz, creating a total throughput of 144.3 Gbits/s. to maintain constant clock latency across all paths, partially configurable delay registers are used. Finally, the partial reconfiguration controller is implemented in hardware to enable fast switch updates.

Partial Run-Time Reconfiguration Using JRTR

Much has been written about the design and performance advantages of partial Run-Time Reconfiguration (RTR) over the last decade. While the results have been promising, commercial support for partial RTR has lagged. Until the introduction of the Xilinx Virtex(tm) family of devices, no mainstream, commercial FPGA has provided support for this capability. In this paper we describe JRTR, a software package which provides direct support for partial run-time reconfiguration. Using a cache-based model, this implementation provides fast, simple support for partial run-time reconfiguration. While the current implementation is on the Xilinx Virtex family of devices using the JBits tool suite, this approach may be applied to any SRAM-based FPGA that provides basic support for RTR.

JBitsTM Implementations of the Advanced Encryption Standard (Rijndael)

The Rijndael algorithm has been selected as the new Advanced Encryption Standard. Several JBits implementations of this algorithm are described which target the VirtexTM FPGA family. As illustrated by sample code, JBits provides a concise means of creating structured datapaths. JBits design abstractions include conventional ones (such as hierarchical modules, ports, nets and buses) and ones that do not appear in structural HDLs (such as layered placement and routing APIs). Unlike mainstream design flows, JBits also permits the exploration of hardware/software tradeoffs for operations such as changing keys and modes, and dynamically modifying the width of key and data blocks. This can significantly reduce the FPGA resource utilization.

VirtexDS: a Virtex device simulator

Until recently FPGAs have been used almost exclusively to implement static circuits. Because FPGAs can be reprogrammed at any time, even in-system at run-time, interest in exploiting this mode of operation has steadily increased. One barrier to widespread use of Run-Time Reconfiguration (RTR) has been the lack of design tools. While tools such as JBits have begun to provide basic support for design entry, traditional verification tools such as simulators have been lacking. This paper discusses VirtexDS, a device level simulator for the Xilinx Virtex (tm) series. The approach taken by VirtexDS is to simulate at the device level, providing an interface which operates much like actual hardware. This approach not only supports simulation for run-time reconfiguration, but also interfaces easily to existing tools. In addition, this low-level simulation approach can provide higher performance than higher-level approaches to simulation.