Priyadarsan Patra

Impact of Process and Temperature Variations on Network-on-Chip Design Exploration

With the continuing scaling of CMOS technologies, process variation is becoming a key factor highly impacting system-level power and temperature. Traditional methods of assuming a uniform temperature and no process variation can lead to gross inaccuracies even for system-level design, thus it is critical to consider the effects of process variation and temperature variation during early design exploration. In this paper, we describe the implementation of an architecture- level early-stage design space exploration tool that incorporates the effect of process and temperature variation for network-on-chips(NoC). The tool is used to study the impact of process and temperature variations on power and energy-delay-product-per-flit metrics for different NoC architectures, and our simulation results show that design choices are influenced by the effects of process and temperature variation, thus demonstrating the importance of considering, and enabling the high- level impact analysis of process and temperature variation early in the design flow.

A design for digital, dynamic clock deskew

Unintentional clock skews between clock domains represent an increasing and costly overhead in high-performance VLSI chips. We describe a novel yet easy-to-implement design that reduces skew between local clock domains dynamically or statically by sensing clock-delay differences and then tuning the clock of each domain relative to its neighbors. Lowering local clock skew is accomplished without compromising worst-case global skew.

Efficient building blocks for delay insensitive circuits

We introduce a new set of primitive elements for delay-insensitive (DI) circuit design. This set is shown to be universal and minimal, that is, any DI circuit can be constructed using only these primitives, and no proper subset of them is sufficient for constructing all such circuits. We give area efficient fast, and robust switch-level implementations of key primitives and show how to use them to construct other DI circuit elements commonly found in the literature.

Delay insensitive logic for RSFQ superconductor technology

Asynchronous designs have been touted as having potential advantages in average performance, power consumption, modularity and tolerance of metastability as compared to traditional synchronous logic. While delay-insensitive (DI) asynchronous circuits are theoretically the most desirable type of asynchronous logic because they make the weakest timing assumptions, the complexity of implementing DI circuits in CMOS or similar technologies may make them impractical to use. The fact that event-based DI circuits are ill matched to CMOS does not necessarily mean that they are inherently inefficient, however. In this paper we show that using Rapid Single Flux Quantum (RSFQ) superconducting circuits, in which information is represented as discrete voltage pulses or magnetic flux quanta, many powerful DI circuit primitives can be implemented at least as efficiently as Boolean logic gates. Since DI logic also alleviates the severe clock skew problems that can be expected at the switching speeds approaching a terahertz in this technology, it may well be a more practical basis for digital circuit design than alternatives traditionally used for CMOS.

Runtime Validation of Transactional Memory Systems

Transactional Memory (TM) has been proposed as a promising solution to effectively harness the increasing processing power of emerging multi/many- core systems. While there has been considerable research on the design and implementation of TM systems, it remains to be shown how to address the validation challenge of such systems in face of increasing design bugs and dynamic errors. This paper proposes a runtime validation methodology for ensuring the end-to-end correctness of a TM system. We use an extended constraint graph model to capture the correctness of a transactional execution, and provide efficient hardware support to perform online checking of this constraint graph. We describe the design ideas as well as the key optimization techniques to make this approach practical. Experiments based on a state-of-the-art TM system framework show that our design effectively performs system-level runtime validation with relatively small overhead.

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study

Fast design space exploration of complex nano-CMOS mixed-signal circuits is an important problem. In this paper, a design process flow that uses metamodels is introduced. In this flow the most important task is the sampling of the design space. In this paper, different sampling techniques for producing an accurate metamodel are investigated to minimize the number of samples required by using a nano-CMOS ring oscillator (RO) as an example. Through SPICE simulations, it is shown that the parasitics have a drastic effect on performance metrics, such as the frequency of oscillation. Alternative sampling techniques, both random, such as Monte Carlo (MC), and uniform, such as Latin Hypercube Sampling (LHS), and Design of Experiments (DOE), are considered as and compared for speed and accuracy. Due to the time constraints of the circuit design process, this paper can be used as a guideline for which sampling technique will produce the most accurate result to minimize the design time. All a experimental results are presented for a 45 nm technology.

ESTIMA: an architectural-level power estimator for multi-ported pipelined register files

We introduce an architectural-level power, area, and latency estimator for multi-ported, pipelined register files. Strengths of the proposed approach include the handling of pipelined operation and clock power, the simulation-based device size estimation, and the ability to handle user-specified timing constraints. The model proposed can be used as a stand-alone estimation and design exploration tool for register files and register-file type structures, or it can be incorporated into a high-level performance simulator to add power estimation capabilities.

A system-level solution to domino synthesis with 2 GHz application

System structure and a taped out 0.18u 2 GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults

Post-silicon validation has emerged as an important component of any chip design methodology to detect both functional and electrical errors that have escaped the pre-silicon validation phase. In order to detect these escaped errors, both controllability and observability factors should be considered. Soft errors and crosstalk faults are two important electrical faults that can adversely affect the correct functionality of the chip. A major bottleneck with the existing approaches is that they do not consider the inter-dependence of the selected trace signals and test generation. In this paper, we explore the synergy between trace signal selection and observability-aware test generation to enable efficient detection of electrical errors including soft errors and crosstalk faults. Our experimental results demonstrate that our approach can significantly improve error detection performance - on an average 58% for crosstalk faults and 48% for soft errors compared to existing techniques.

Efficient delay-insensitive RSFQ circuits

It is reasonable to project that continuing progress in micro-electronics will lead to computing systems based on circuit elements with switching times on the order of a few picaseconds. Such speeds are likely beyond the capabilities of CMOS. One promising technology is Rapid Single Flux Quantum (RSFQ) circuits based on super-conducting Josephson junction devices. However, for such high-speed technologies, clock skew even over short distances can make synchronous circuit design prohibitively difficult. We have introduced a variant of delay insensitive (DI) asynchronous logic called conservative delay insensitive (CDI) logic which has particularly nice properties for use in RSFQ technology. Not only does it solve high-speed clocking problems, but its primitive elements appear to be more efficiently implementable in RSFQ technology than are traditional Boolean logic primitives and its property of minimizing the creation and destruction of signal pulses avoids some difficult implementation issues in RSFQ.