Brad Smith

A novel biasing technique for addressable parametric arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 times 32 and 4 times 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence.

A Novel Biasing Technique for Addressable Parametric Arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that removes the drain-source bias from these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted more than a two-decade drop in parasitic leakage of the array. Experiment data performed on a 90 nm technology confirmed this improvement.

Calibration of library element optimization to improve static power

Library elements (or standard cells) are basic building blocks of integrated circuits. These are built early in the technology cycle. Small changes to library elements can result in significant power/performance changes to large designs instantiating them. Qualifying these small changes on silicon can benefit products. Several physical layout optimizations are performed to improve performance and/or reduce standby power. This paper demonstrates the application of ring oscillators to calibrate such optimizations. These ring oscillators are designed to provide cell-specific validation and feedback to the entire library optimization. Silicon calibration results from 55nm technology node are discussed.

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

The stress-inducing effects of neighboring metal interconnect features were studied using novel stressmigration test structures with various layouts of perpendicular neighboring combs. The structures with narrow widths showed no change in stressmigration performance, with or without near-neighbor structures. However, structures built with wider lines showed up to 3X worse stressmigration performance when perpendicular combs were present nearby, essentially independent of the spacing to the combs. Thus, near neighbor metal features were shown to be capable of degrading SM performance in some lines.

Efficient technique for Si validation of level shifters

This paper presents a new structure that uses an addressable parametric array to validate level shifter cells. This structure is very area efficient and allows direct measurement of input and output voltages. Being a parametric structure enabled direct measurement of the output voltages, a critical parameter for level shifters. Experimental data confirmed the utility of this approach, validating level shifters in three different power domains including source biasing on the same 22-pad design. The simulation results show good correlation with the measured data.

A versatile defectivity monitor designed for efficient test and failure analysis

This paper describes development, design, and test of a short flow defectivity monitor. Careful considerations were given to size the structures and to arrange them in a fashion that allows both efficient test and efficient failure analysis. Test time was saved by using a two-step probe method. A coarse pass was used to test wafers for defects. Then specific defects were localized with additional testing.