Kulbhushan Misri

A single supply level shifter for multi-voltage systems

This paper presents design and application of a level shifter circuit which works with a single power supply. Unlike the conventional level shifter circuits, the proposed level shifter can shift any voltage level signal to a desired higher level without any leakage current. Use of single supply level shifter greatly reduces the supply routing and layout congestion within the chip when level shifting is required between different voltage domains. It also reduces pin count if level shifting is required between two or more chips operating at different supply voltages in a multi-voltage system. The proposed circuit is generic in nature and the voltage range at which level shifting can be done is limited by the technology only. The circuits was designed in 90nm CMOS technology and simulated in SPICE. The simulation results show that the proposed level shifter circuit is able to shift the input signal from 1.2V to 2.5V at maximum frequency of 500MHz.

Low power startup circuits for voltage and current reference with zero steady state current

A class of new startup circuits for Voltage and Current Reference circuits are proposed. Unlike conventional startup circuits, the proposed circuits completely turn off once the reference circuit is started and consume no current during normal operation of the reference circuits. The circuits employ feedback from the reference circuit to ensure that the reference circuit has reached its desired operating state prior to shutting themselves off. The proposed circuits are quite useful in low power integrated circuit design. Very low startup time can be achieved. The circuits are generic in nature and can be used with any reference circuit such as bandgap voltage reference, ΔVgs/R circuit, etc.

Techniques for on-chip process voltage and temperature detection and compensation

This paper presents techniques to detect process, voltage and temperature (PVT) variations in an integrated circuit chip and wafer. Conventional techniques are limited to detection of process variations in which the MOS devices (NMOS and PMOS) move in similar direction i.e. fast n-fast p or slow n-slow p. The presented techniques can be used to compensate skewed variations on the chip i.e. fast n-slow p or slow n-fast p thus increasing the utilization (yield) of the wafer. The proposed techniques can be implemented in any standard CMOS process and can easily be integrated with any circuit requiring PVT compensation. Major applications of these circuits are in I/O drivers and PVT sensitive analog circuits. For I/O drivers, simulation results show that the rise/fall time variation with PVT has been reduced to more than half using the proposed circuits.

A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature

A low voltage switched-capacitor circuit that generates an almost constant reference current across process, voltage and temperature (PVT) is proposed. The reference voltage is generated by a low voltage band-gap circuit. The output reference current is obtained by applying the generated reference voltage to a low voltage V-I converter. The resistor in the proposed V-I converter is further replaced by a switched capacitor resistor. Due to less variation in the capacitor value across PVTs and high accuracy in integrated voltage reference, the output reference current remains fairly constant. The circuit has been designed in 0.13 /spl mu/m CMOS process at 1.5 V supply voltage. The simulation results show that the output reference current is quite insensitive to PVT and varies linearly with clock frequency and capacitor value of the switched capacitor resistor.

A tunable g/sub m/-C filter with low variation across process, voltage and temperature

A tunable g/sub m/-C filter with cutoff frequency insensitive to Process, Voltage and Temperature is proposed. An external clock frequency is used to generate a current using a switched capacitor circuit. The proposed filter is ideally suited for applications where a tight control on cutoff frequency is desired across different operating conditions of the chip. The circuit was designed in 3.3 V BiCMOS technology and simulations were carried out using SPICE. The simulation results show that the total variation in the cutoff frequency is 1% as compared to the 27% variation in conventional g/sub m/-C filter over the temperature range of -40 to 120 degC. The variation across process corners is 2.4% and is almost independent of the capacitor variation due to process and temperature.