Sanjay K. Wadhwa

A single supply level shifter for multi-voltage systems

This paper presents design and application of a level shifter circuit which works with a single power supply. Unlike the conventional level shifter circuits, the proposed level shifter can shift any voltage level signal to a desired higher level without any leakage current. Use of single supply level shifter greatly reduces the supply routing and layout congestion within the chip when level shifting is required between different voltage domains. It also reduces pin count if level shifting is required between two or more chips operating at different supply voltages in a multi-voltage system. The proposed circuit is generic in nature and the voltage range at which level shifting can be done is limited by the technology only. The circuits was designed in 90nm CMOS technology and simulated in SPICE. The simulation results show that the proposed level shifter circuit is able to shift the input signal from 1.2V to 2.5V at maximum frequency of 500MHz.

Low power startup circuits for voltage and current reference with zero steady state current

A class of new startup circuits for Voltage and Current Reference circuits are proposed. Unlike conventional startup circuits, the proposed circuits completely turn off once the reference circuit is started and consume no current during normal operation of the reference circuits. The circuits employ feedback from the reference circuit to ensure that the reference circuit has reached its desired operating state prior to shutting themselves off. The proposed circuits are quite useful in low power integrated circuit design. Very low startup time can be achieved. The circuits are generic in nature and can be used with any reference circuit such as bandgap voltage reference, ΔVgs/R circuit, etc.

Programmable Digital Frequency Multiplier

A programmable digital frequency multiplier with wide multiplication factor range and low lock time is presented. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in voltage and temperature during circuit operation. The circuit has been designed in 90 nm CMOS process for input reference frequency of 32.768 KHz and multiplication factor range of 128 to 1023. The silicon results show less than 2% of average frequency error at maximum multiplication factor.

Zero steady state current power-on-reset circuit with brown-out detector

A novel power on reset (POR) circuit with brown out (BO) detector having zero steady state current consumption is proposed. The circuit has been designed in 65nm CMOS process at a single supply of 1.1V. Both the POR and BO thresholds are independently adjustable in the circuit. Simulation results show that the POR threshold does not depend upon the supply ramp-rate at fixed process and temperature corner. BO circuit works for a large range of supply ramp down rates. Due to zero steady state current consumption, the proposed circuit is well suited for low power applications.

A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature

A low voltage switched-capacitor circuit that generates an almost constant reference current across process, voltage and temperature (PVT) is proposed. The reference voltage is generated by a low voltage band-gap circuit. The output reference current is obtained by applying the generated reference voltage to a low voltage V-I converter. The resistor in the proposed V-I converter is further replaced by a switched capacitor resistor. Due to less variation in the capacitor value across PVTs and high accuracy in integrated voltage reference, the output reference current remains fairly constant. The circuit has been designed in 0.13 /spl mu/m CMOS process at 1.5 V supply voltage. The simulation results show that the output reference current is quite insensitive to PVT and varies linearly with clock frequency and capacitor value of the switched capacitor resistor.

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from −40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.

A low voltage CMOS bandgap reference circuit

A CMOS low voltage bandgap reference circuit is presented. The proposed circuit architecture enables it to work with supply voltages as low as 1.1 V. The circuit is designed in 90 nm CMOS technology for a typical bandgap output voltage of 611 mV. Simulation results show that generated bandgap output voltage varies from 600 mV to 626 mV across all possible combinations of MOSFET, resistor, BJT, supply voltage and temperature variation corners. Simulation results have been given for a wide temperature variation from -40C to 125C and supply voltage variation from 1.1 V to 1.3 V.

A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference

A CMOS low voltage Proportional-to-Absolute Temperature current reference is presented. The proposed circuit can work with supply voltages as low as 1.1V. The circuit is designed in 90nm CMOS technology for 2.2µA reference current at typical corner, 27C, 1.2V. The circuit has been extensively simulated across all possible combinations of MOSFET, Resistor, BJT, supply voltage and temperature variation corners. Simulation results have been given for a wide temperature variation from -40C to 125C and supply voltage variation from 1.1V to 1.3V.

A tunable g/sub m/-C filter with low variation across process, voltage and temperature

A tunable g/sub m/-C filter with cutoff frequency insensitive to Process, Voltage and Temperature is proposed. An external clock frequency is used to generate a current using a switched capacitor circuit. The proposed filter is ideally suited for applications where a tight control on cutoff frequency is desired across different operating conditions of the chip. The circuit was designed in 3.3 V BiCMOS technology and simulations were carried out using SPICE. The simulation results show that the total variation in the cutoff frequency is 1% as compared to the 27% variation in conventional g/sub m/-C filter over the temperature range of -40 to 120 degC. The variation across process corners is 2.4% and is almost independent of the capacitor variation due to process and temperature.

High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFet

A CMOS bandgap reference (BGR) circuit with low mismatch spread is proposed. A conventional BGR circuit uses a CMOS error amplifier and its input offset causes large spread in the bandgap output voltage. The proposed BGR circuit does not use a separate error amplifier. Instead, the bipolar transistor pair used to generate ΔVbe acts as input differential pair as well resulting in low mismatch spread. It can generate the typical 1.22V as well as any number of less than 1.22V bandgap outputs simultaneously without requiring a separate voltage divider circuit. As compared to other offset reduction techniques such as chopping which require a clock and extra area, the proposed BGR circuit is very simple to implement. The proposed BGR circuit has been designed in 16nm FinFet technology for a wide temperature range of -40°C to 125°C and supply voltage range of 1.8V ± 10%. The post-layout extracted simulation results and silicon characterization results are in close agreement. The silicon results show that the maximum peak to peak variation is 8mV or 1.3% for a bandgap output of 0.605V. The proposed BGR consumes 340µW power at 1.8V.