Qin Jun-Rui

Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

Heavy ion experiments on 65 nm bulk CMOS inverter chains demonstrate the impact of circuit placement on single-event transients (SETs). Experimental data and simulations show that the horizontal placement design significantly reduces the SET pulse width and SET cross-section compared to the vertical placement design due to the existence of pulse quenching.

A novel layout for single event upset mitigation in advanced CMOS SRAM cells

A novel layout has been proposed to reduce the single event upset (SEU) vulnerability of SRAM cells. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors. For the angle incidence, the proposed layout is immune from ion hit in two plans, and is more robust against SEU in other two plans than the conventional one. The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%. Consequently, the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

The effect of P + deep well doping on SET pulse propagation

The change of P+ deep well doping will affect the charge collection of the active and passive devices in nano-technology, thus affecting the propagated single event transient (SET) pulsewidths in circuits. The propagated SET pulsewidths can be quenched by reducing the doping of P+ deep well in the appropriate range. The study shows that the doping of P+ deep well mainly affects the bipolar amplification component of SET current, and that changing the P+ deep well doping has little effect on NMOS but great effect on PMOS.

Recovery of single event upset in advanced complementary metal—oxide semiconductor static random access memory cells

Using computer-aided design three-dimensional (3D) simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer (LET) threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability.

Parasitic bipolar amplification in a single event transient and its temperature dependence

Using three-dimensional technology computer-aided design (TCAD) simulation, parasitic bipolar amplification in a single event transient (SET) current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both 130-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor.

Temperature and drain bias dependence of single event transient in 25-nm FinFET technology

In this paper, we investigate the temperature and drain bias dependency of single event transient (SET) in 25-nm fin field-effect-transistor (FinFET) technology in a temperature range of 0–135 °C and supply voltage range of 0.4 V–1.6 V. Technology computer-aided design (TCAD) three-dimensional simulation results show that the drain current pulse duration increases from 0.6 ns to 3.4 ns when the temperature increases from 0 to 135 °C. The charge collected increases from 45.5 fC to 436.9 fC and the voltage pulse width decreases from 0.54 ns to 0.18 ns when supply voltage increases from 0.4 V to 1.6 V. Furthermore, simulation results and the mechanism of temperature and bias dependency are discussed.

The supply voltage scaled dependency of the recovery of single event upset in advanced complementary metal—oxide—semiconductor static random-access memory cells

Using computer-aided design three-dimensional simulation technology, the supply voltage scaled dependency of the recovery of single event upset and charge collection in static random-access memory cells are investigated. It reveals that the recovery linear energy transfer threshold decreases with the supply voltage reducing, which is quite attractive for dynamic voltage scaling and subthreshold circuit radiation-hardened design. Additionally, the effect of supply voltage on charge collection is also investigated. It is concluded that the supply voltage mainly affects the bipolar gain of the parasitical bipolar junction transistor (BJT) and the existence of the source plays an important role in supply voltage variation.

The temperature dependence of single-event transients in 90-nm CMOS dual-well and triple-well NMOSFETs

This paper investigates the temperature dependence of single-event transients (SETs) in 90-nm complementary metal—oxide semiconductor (CMOS) dual-well and triple-well negative metal—oxide semiconductor field-effect transistors (NMOSFETs). Technology computer-aided design (TCAD) three-dimensional (3D) simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from −55 °C to 125 °C, which is closely correlated with the NMOSFET sources. This reveals that the pulse width increases with temperature in dual-well due to the weakening of the anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.

Effect of body biasing on single-event induced charge collection in deep N-well technology

As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits (ICs). At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design (TCAD) simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.