Qixiang Cheng

Software-defined networking control plane for seamless integration of multiple silicon photonic switches in Datacom networks

Silicon photonics based switches offer an effective option for the delivery of dynamic bandwidth for future large-scale Datacom systems while maintaining scalable energy efficiency. The integration of a silicon photonics-based optical switching fabric within electronic Datacom architectures requires novel network topologies and arbitration strategies to effectively manage the active elements in the network. We present a scalable software-defined networking control plane to integrate silicon photonic based switches with conventional Ethernet or InfiniBand networks. Our software-defined control plane manages both electronic packet switches and multiple silicon photonic switches for simultaneous packet and circuit switching. We built an experimental Dragonfly network testbed with 16 electronic packet switches and 2 silicon photonic switches to evaluate our control plane. Observed latencies occupied by each step of the switching procedure demonstrate a total of 344 µs control plane latency for data-center and high performance computing platforms.

Photonic switching in high performance datacenters [Invited]

Photonic switches are increasingly considered for insertion in high performance datacenter architectures to meet the growing performance demands of interconnection networks. We provide an overview of photonic switching technologies and develop an evaluation methodology for assessing their potential impact on datacenter performance. We begin with a review of three categories of optical switches, namely, free-space switches, III-V integrated switches and silicon integrated switches. The state-of-the-art of MEMS, LCOS, SOA, MZI and MRR switching technologies are covered, together with insights on their performance limitations and scalability considerations. The performance metrics that are required for optical switches to truly emerge in datacenters are discussed and summarized, with special focus on the switching time, cost, power consumption, scalability and optical power penalty. Furthermore, the Pareto front of the switch metric space is analyzed. Finally, we propose a hybrid integrated switch fabric design using the III-V/Si wafer bonding technique and investigate its potential impact on realizing reduced cost and power penalty.

Challenges and solutions for high-volume testing of silicon photonics

The first generation of silicon photonic products is now commercially available. While silicon photonics possesses key economic advantages over classical photonic platforms, it has yet to become a commercial success because these advantages can be fully realized only when high-volume testing of silicon photonic devices is made possible. We discuss the costs, challenges, and solutions of photonic chip testing as reported in the recent research literature. We define and propose three underlying paradigms that should be considered when creating photonic test structures: Design for Fast Coupling, Design for Minimal Taps, and Design for Parallel Testing. We underline that a coherent test methodology must be established prior to the design of test structures, and demonstrate how an optimized methodology dramatically reduces the burden when designing for test, by reducing the needed complexity of test structures.

Recent advances in optical technologies for data centers: a review

Modern data centers increasingly rely on interconnects for delivering critical communications connectivity among numerous servers, memory, and computation resources. Data center interconnects turned to optical communications almost a decade ago, and the recent acceleration in data center requirements is expected to further drive photonic interconnect technologies deeper into the systems architecture. This review paper analyzes optical technologies that will enable next-generation data center optical interconnects. Recent progress addressing the challenges of terabit/s links and networks at the laser, modulator, photodiode, and switch levels is reported and summarized.

Highly-scalable, low-crosstalk architecture for ring-based optical space switch fabrics

A ring-based switch architecture that combines the Clos network with populated switch-and-select stages is proposed, achieving significantly reduced crosstalk compared to other non-blocking architectures. Detailed physical-layer simulation results show a 128×128 switch exhibits a power penalty of 18dB, improving >10dB compared to the Benes switch.