Meisam Bahadori

Comprehensive Design Space Exploration of Silicon Photonic Interconnects

The paper presents a comprehensive physical layer design and modeling platform for silicon photonic interconnects. The platform is based on explicit closed-form expressions for optical power penalties, derived for both signal-dependent and signal-independent noise contexts. Our models agree well with reported experimental measurements. We show how the modeling approach is used for the design space exploration of silicon photonic links and can be leveraged to optimize the wavelength-division multiplexed (WDM) capacity, evaluate the scalability, and study the sensitivity of the system to key device parameters. We apply the methodology to the design of microring-based silicon photonic links, including an evaluation of the impairments associated with cascaded ring modulators, as well as the spectral distortion and crosstalk effects of demultiplexer ring arrays for nonreturn-to-zero (NRZ) ON-OFF keying (OOK) modulated WDM signals. We show that the total capacity of a chip-to-chip microring-based WDM silicon photonic link designed with recently reported interconnect device parameters can approach 2 Tb/s realized with NRZ-OOK data modulation and 45 wavelengths each modulated at 45 Gb/s.

Optimization of microring-based filters for dense WDM silicon photonic interconnects

The article describes an experimentally validated approach for optimizing wavelength-selective microring filters based on optical signals power penalties. The methodology is used to analyze the performance of WDM links for various bit rates and channel-spacing.

Crosstalk Penalty in Microring-Based Silicon Photonic Interconnect Systems

We examine inter-channel and intra-channel crosstalk power penalties between non-return-to-zero on-off keying (NRZ-OOK) wavelength-division-multiplexing (WDM) channels for microring-based silicon photonic interconnects. We first propose a new model that relates the crosstalk power penalty to the interfering signals power, the extinction ratio of the non-return-to-zero, OOK modulated “victim” channel, and finally the bit-error-ratio that the power penalty is referenced to. As for inter-channel crosstalk, the proposed model agrees well with our recent experimental measurements. We leverage this model to quantify crosstalk induced power penalties in a microring based WDM receiver. We also propose an optimization procedure to equilibrate the power penalty across channels. We then compare our model with intra-channel crosstalk measurements, where two NRZ channels are at the same wavelength and are simultaneously routed to different paths by two cascaded ring resonators. We remark that intra-channel crosstalk is very sensitive to the data rate of NRZ channels. As data rate increases, the observed disturbances exceed what models predict. Based on these observations, we propose an empirical modification of the original model for estimating intra-channel crosstalk power penalties in high (>20 Gb/s) data rate situations.

Flexfly: enabling a reconfigurable dragonfly through silicon photonics

The Dragonfly topology provides low-diameter connectivity for high-performance computing with all-to-all global links at the inter-group level. Our traffic matrix characterization of various scientific applications shows consistent mismatch between the imbalanced group-to-group traffic and the uniform global bandwidth allocation of Dragonfly. Though adaptive routing has been proposed to utilize bandwidth of non-minimal paths, increased hops and cross-group interference lower efficiency. This work presents a photonic architecture, Flexfly, which “trades” global links among groups using low-radix Silicon photonic switches. With transparent optical switching, Flexfly reconfigures the inter-group topology based on traffic pattern, stealing additional direct bandwidth for communication-intensive group pairs. Simulations with applications such as GTC, Nekbone and LULESH show up to 1.8× speedup over Dragonfly paired with UGAL routing, along with halved hop count and latency for cross-group messages. We built a 32-node Flexfly prototype using a Silicon photonic switch connecting four groups and demonstrated 820 ns interconnect reconfiguration time.

Optical interconnects for extreme scale computing systems

Face-to-face comparison of major large scale HPC interconnects.Review of challenges and solutions for increased use of optics in HPC.Description of optical switching, in terms of principle, limitations, technical requirements and benefits. Large-scale high performance computing is permeating nearly every corner of modern applications spanning from scientific research and business operations, to medical diagnostics, and national security. All these communities rely on computer systems to process vast volumes of data quickly and efficiently, yet progress toward increased computing power has experienced a slowdown in the last number of years. The sheer cost and scale, stemming from the need for extreme parallelism, are among the reasons behind this stall. In particular, very large-scale, ultra-high bandwidth interconnects, essential for maintaining computation performance, represent an increasing portion of the total cost budget.Photonic systems are often cited as ways to break through the energy-bandwidth limitations of conventional electrical wires toward drastically improving interconnect performance. This paper presents an overview of the challenges associated with large-scale interconnects, and reviews how photonic technologies can contribute to addressing these challenges. We review some important aspects of photonics that should not be underestimated in order to truly reap the benefits of cost and power reduction.

Software-defined control-plane for wavelength selective unicast and multicast of optical data in a silicon photonic platform

We demonstrate a programmable control-plane based on field programmable gate array (FPGA) with a power-efficient algorithm for optical unicast, multicast, and broadcast functionalities in a silicon photonic platform. The platform includes a silicon photonic 1×8 microring array chip which in conjunction with a fast tunable laser over the C-band is capable of delivering software controlled wavelength selective functionality on top of spatial switching. We characterize the thermo-optic response of microring resonators and extract key parameters necessary for the development of the control-plane. The performance of the proposed architecture is tested with 10 Gb/s on-off keying (OOK) optical data and error-free operation is verified for various wavelength and spatial switching scenarios. Lastly, we evaluate electrical power and energy consumption required to reconfigure the silicon photonic device for all possible wavelength operations and output ports combinations and show that unicast, multicast of two, three, four, five, six, seven, and broadcast functions are achieved with energy overheads of 0.02, 0.07, 0.18, 0.49, 0.76, 1.01, 1.3, and 1.55 pJ/bit, respectively.

PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects

Silicon Photonics is emerging as a key technology for high-performance computing interconnects. Yet few tools are available to investigate how to best leverage this technology in current or future computer architectures and, furthermore, how this technology will impact real application workloads. In this paper, we present a multi-layer simulation and modeling software solution -- PhoenixSim. PhoenixSim enables integrated and interactive design space exploration over the physical, networking and application layers. In this paper, we report its general organization and constituting models. We show how the different layers of the tool can be utilized to design and analyze an optical interconnect network for supporting the HPCG (High Performance Conjugate Gradient) benchmark.

Energy-performance optimized design of silicon photonic interconnection networks for high-performance computing

We present detailed electrical and optical models of the elements that comprise a WDM silicon photonic link. The electronics is assumed to be based on 65 nm CMOS node and the optical modulators and demultiplexers are based on microring resonators. The goal of this study is to analyze the energy consumption and scalability of the link by finding the right combination of (number of channels × data rate per channel) that fully covers the available optical power budget. Based on the set of empirical and analytical models presented in this work, a maximum capacity of 0.75 Tbps can be envisioned for a point-to-point link with an energy consumption of 1.9 pJ/bit. Sub-pJ/bit energy consumption is also predicted for aggregated bitrates up to 0.35 Tbps.

Energy-bandwidth design exploration of silicon photonic interconnects in 65nm CMOS

Exploration of energy-bandwidth tradeoffs is performed for a silicon photonic link, showing a maximum capacity of 1.9 Tb/s with an energy cost of 1.54 pJ/bit at 13 Gb/s signaling rate. We conclude that 10 Gb/s yields a good trade-off between throughput and energy efficiency.

Photonic switching in high performance datacenters [Invited]

Photonic switches are increasingly considered for insertion in high performance datacenter architectures to meet the growing performance demands of interconnection networks. We provide an overview of photonic switching technologies and develop an evaluation methodology for assessing their potential impact on datacenter performance. We begin with a review of three categories of optical switches, namely, free-space switches, III-V integrated switches and silicon integrated switches. The state-of-the-art of MEMS, LCOS, SOA, MZI and MRR switching technologies are covered, together with insights on their performance limitations and scalability considerations. The performance metrics that are required for optical switches to truly emerge in datacenters are discussed and summarized, with special focus on the switching time, cost, power consumption, scalability and optical power penalty. Furthermore, the Pareto front of the switch metric space is analyzed. Finally, we propose a hybrid integrated switch fabric design using the III-V/Si wafer bonding technique and investigate its potential impact on realizing reduced cost and power penalty.