Robert Polster

Optical interconnects for extreme scale computing systems

Face-to-face comparison of major large scale HPC interconnects.Review of challenges and solutions for increased use of optics in HPC.Description of optical switching, in terms of principle, limitations, technical requirements and benefits. Large-scale high performance computing is permeating nearly every corner of modern applications spanning from scientific research and business operations, to medical diagnostics, and national security. All these communities rely on computer systems to process vast volumes of data quickly and efficiently, yet progress toward increased computing power has experienced a slowdown in the last number of years. The sheer cost and scale, stemming from the need for extreme parallelism, are among the reasons behind this stall. In particular, very large-scale, ultra-high bandwidth interconnects, essential for maintaining computation performance, represent an increasing portion of the total cost budget.Photonic systems are often cited as ways to break through the energy-bandwidth limitations of conventional electrical wires toward drastically improving interconnect performance. This paper presents an overview of the challenges associated with large-scale interconnects, and reviews how photonic technologies can contribute to addressing these challenges. We review some important aspects of photonics that should not be underestimated in order to truly reap the benefits of cost and power reduction.

End-to-End Modeling and Optimization of Power Consumption in HPC Interconnects

The Interconnect topology is one of the key design choices of large-scale distributed computer architectures. It might also become one of the most power consuming design elements as traffic volumes and interconnect size continue to grow. High interconnect power consumption can be simply provoked by non-energy efficient components, or can in contrast be due to architectural misconception. In this paper, we propose and combine various high-level models to realize a clear breakdown of the power consumptions, and analyze how these depend on various parameters, either external or internal, to the interconnect. Our initial results indicate that end-to-end interconnect consumption is dominated by routers. The node compute power can also affect the interconnect energy efficiency, especially if links of equal bandwidth are used as injection links and topology inner links.

Energy-performance optimized design of silicon photonic interconnection networks for high-performance computing

We present detailed electrical and optical models of the elements that comprise a WDM silicon photonic link. The electronics is assumed to be based on 65 nm CMOS node and the optical modulators and demultiplexers are based on microring resonators. The goal of this study is to analyze the energy consumption and scalability of the link by finding the right combination of (number of channels × data rate per channel) that fully covers the available optical power budget. Based on the set of empirical and analytical models presented in this work, a maximum capacity of 0.75 Tbps can be envisioned for a point-to-point link with an energy consumption of 1.9 pJ/bit. Sub-pJ/bit energy consumption is also predicted for aggregated bitrates up to 0.35 Tbps.

Energy-bandwidth design exploration of silicon photonic interconnects in 65nm CMOS

Exploration of energy-bandwidth tradeoffs is performed for a silicon photonic link, showing a maximum capacity of 1.9 Tb/s with an energy cost of 1.54 pJ/bit at 13 Gb/s signaling rate. We conclude that 10 Gb/s yields a good trade-off between throughput and energy efficiency.

Challenges and solutions for high-volume testing of silicon photonics

The first generation of silicon photonic products is now commercially available. While silicon photonics possesses key economic advantages over classical photonic platforms, it has yet to become a commercial success because these advantages can be fully realized only when high-volume testing of silicon photonic devices is made possible. We discuss the costs, challenges, and solutions of photonic chip testing as reported in the recent research literature. We define and propose three underlying paradigms that should be considered when creating photonic test structures: Design for Fast Coupling, Design for Minimal Taps, and Design for Parallel Testing. We underline that a coherent test methodology must be established prior to the design of test structures, and demonstrate how an optimized methodology dramatically reduces the burden when designing for test, by reducing the needed complexity of test structures.

10 Gbps, 560 fJ/b TIA and modulator driver for optical networks-on-chip in CMOS 65nm

This work presents the front-end electronics of a 10 Gbps optical link for network-on-chip applications based on silicon photonic components. The Rx TIA does not require input DC current compensation and achieves a record gain-bandwidth/power FoM of 150 THzΩ/mW, resulting in 23 fJ/bit of consumption for 2.3 kΩ of transimpedance. The Tx modulator driver is able to drive a 70 fF resonant ring modulator with 2.4 Vpp swing achieving an efficiency of 537 fJ/bit.

A TIA for optical networks-on-chip in 65nm CMOS

We present a 260μW, 1 kΩ to 18 kΩ transimpedance amplifier. We measured high bandwidth up to 17 GHz and demonstrate the functionality as a receiver-front-end optimized for large DC input range multiple-writer single-reader links.