Qizhi Liu

Total Dose and Transient Response of SiGe HBTs from a New 4th-Generation, 90 nm SiGe BiCMOS Technology

The total ionizing dose and laser-induced transient response of a new 4th generation 90 nm IBM SiGe 9HP technology are investigated. Total dose testing was performed with 63.3 MeV protons at the Crocker Nuclear Laboratory at the University of California, Davis. Transient testing was performed on the two-photon absorption system at Naval Research Laboratory. Results show that the SiGe HBTs are dose-tolerant up to 3 Mrad(SiO2) and exhibit reduced single event transients compared to earlier SiGe generations.

A 0.35 μm SiGe BiCMOS technology for power amplifier applications

In this paper we introduce, a state-of-the-art SiGe BiCMOS power amplifier technology that features two NPNs with 40 GHz / 6.0 V & 27 GHz / 8.5 V (fT - BVceo) respectively, a novel low inductance metal ground through-silicon-via (TSV), integrated on a low-cost 0.35 μm lithography node with 3.3 V / 5.0 V dual-gate CMOS technology and high-quality passives on a 50 Ω.cm substrate.

Study of mutual and self-thermal resistance in 90nm SiGe HBTs

Impact of mutual thermal coupling on the performance of a single 90nm SiGe heterojunction bipolar transistor (HBT) due to the presence of power dissipating elements like other HBTs in near vicinity is presented in this paper. Mutual thermal resistance (Rth,mutual) has been computed as a function of spacing between the single HBT and a ring of HBTs surrounding the device. HBT structural design variations including device layout schemes, metal wire stack connected to the emitter, deep trench (DT) depth and emitter to DT spacing, for reduced self thermal resistance (Rth), have been explored in this paper. An updated thermal resistance model accounting for the heat flow through the metal wiring stack connected to the emitter is also reported.

Schottky Barrier Diodes in 90nm SiGe BiCMOS process operating near 2.0 THz cut-off frequency

High performance Schottky Barrier Diodes (SBDs) with cut-off frequency (fc) ~2.0 THz integrated into a 90nm SiGe BiCMOS technology for millimeter wave (mm-wave) applications are presented in this paper. To our knowledge, this is the highest reported fc for a SBD in a BiCMOS technology. The SBDs reported here have low reverse bias leakage with breakdown voltage of ~5V, and have been integrated in the base technology without the addition of any extra processing step. The affects of variation of critical process and device parameters - undoped silicon layer (n-epi) thickness, thermal cycle associated with deep-trench formation, cathode reach-through width, and anode area on device performance have also been investigated and are presented here.

Co-integration of high-performance and high-breakdown SiGe HBTs in a BiCMOS technology

Having two, or more, transistors with different values of fT and BVCEO provides flexibility to circuit designers in making tradeoffs of power and performance. The process complexity and resulting cost of fabricating these transistors on the same wafer is another important factor. Three different approaches for co-integrating high-performance and high-breakdown SiGe npn HBTs with minimal process deviation are presented herein. The work features a high-performance HBT with fT × BVCEO product of 500GHz-V and a high-breakdown HBT with over 430GHz-V integrated on the same wafer with one-mask deviation.

A novel Ccb and Rb reduction technique for high-speed SiGe HBTs

In this paper, we discuss a novel technique to reduce base resistance (R_b) and collector-base capacitance (C_cb) for higher F_max in high-speed SiGe HBTs. In order to reduce C_cb, we first located the origins of the different components of C_cb through AC extraction. Then we utilized scanning capacitance measurements (SCM) to examine the shape of the collector-base depletion. We then propose a method to reduce the extrinsic C_cb, namely by using reticle enhancement techniques to print a blocking oxide layer to inhibit boron outdiffusion. An additional benefit was the reduction of R_b by reducing the base link resistance.

Investigation of HBT layout impact on f T doubler performance for 90nm SiGe HBTs

Peak fT of 660 GHz is reported for HBT fT doubler designs in IBM 90 nm SiGe BiCMOS technology 9HP. This high performance fT doubler utilizes a longer HBT for output stage compared to the input stage HBT (length ratio 2:1) resulting in improved transconductance and lower thermal resistance. The impact of HBT layout on the circuit performance and trade-off between thermal resistance and fT is also investigated. fT doubler circuit can be used as a single transistor in several circuit applications like A/D converters and broadband circuits where higher performance is desired.

Modeling of U-shaped and plugged emitter resistance of high speed SiGe HBTs

In this paper, we investigate the emitter resistance R<inf>e</inf> in SiGe HBTs with speeds up to 280GHz, using a U-shaped polysilicon emitter. We observed that R<inf>e</inf> increased with lateral scaling, thereby degrading f<inf>T</inf>. Although a negligible component in the past, in this experiment R<inf>e</inf> * C<inf>cb</inf> transit time delay is playing a more significant role in limiting f<inf>T</inf>. R<inf>e</inf> was modeled to explain the increase due to lateral scaling, and was shown to result from the plugging of the emitter opening by the emitter polysilicon. Furthermore, process experiments were conducted to investigate the effect of emitter polysilicon thickness, sidewall height, and emitter i-layer thickness.