James W. Adkisson

A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBMs large volume 200mm fabrication line. The technology features 300 GHz fT and 360 GHz fMAX high performance SiGe HBTs, 135 GHz fT and 2.5V BVCEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

Total Dose and Transient Response of SiGe HBTs from a New 4th-Generation, 90 nm SiGe BiCMOS Technology

The total ionizing dose and laser-induced transient response of a new 4th generation 90 nm IBM SiGe 9HP technology are investigated. Total dose testing was performed with 63.3 MeV protons at the Crocker Nuclear Laboratory at the University of California, Davis. Transient testing was performed on the two-photon absorption system at Naval Research Laboratory. Results show that the SiGe HBTs are dose-tolerant up to 3 Mrad(SiO2) and exhibit reduced single event transients compared to earlier SiGe generations.

CMOS Imager with Copper Wiring and Lightpipe

A CMOS imager technology is described, which uses Cu wiring and a polymer lightpipe. The microlens height must be optimized when using the lightpipe, so that light is focused into the top of the lightpipe rather than onto the photodiode. A SiN layer is used on the sidewalls to reflect light that enters the top of the lightpipe down onto the photodiode. The SiN layer also forms a hermetic seal, which protects the Cu wiring from ambient moisture. Using this structure, high quantum efficiency can be achieved for a 2.2 mum pixel and high reliability is demonstrated

Study of mutual and self-thermal resistance in 90nm SiGe HBTs

Impact of mutual thermal coupling on the performance of a single 90nm SiGe heterojunction bipolar transistor (HBT) due to the presence of power dissipating elements like other HBTs in near vicinity is presented in this paper. Mutual thermal resistance (Rth,mutual) has been computed as a function of spacing between the single HBT and a ring of HBTs surrounding the device. HBT structural design variations including device layout schemes, metal wire stack connected to the emitter, deep trench (DT) depth and emitter to DT spacing, for reduced self thermal resistance (Rth), have been explored in this paper. An updated thermal resistance model accounting for the heat flow through the metal wiring stack connected to the emitter is also reported.

Schottky Barrier Diodes in 90nm SiGe BiCMOS process operating near 2.0 THz cut-off frequency

High performance Schottky Barrier Diodes (SBDs) with cut-off frequency (fc) ~2.0 THz integrated into a 90nm SiGe BiCMOS technology for millimeter wave (mm-wave) applications are presented in this paper. To our knowledge, this is the highest reported fc for a SBD in a BiCMOS technology. The SBDs reported here have low reverse bias leakage with breakdown voltage of ~5V, and have been integrated in the base technology without the addition of any extra processing step. The affects of variation of critical process and device parameters - undoped silicon layer (n-epi) thickness, thermal cycle associated with deep-trench formation, cathode reach-through width, and anode area on device performance have also been investigated and are presented here.

Co-integration of high-performance and high-breakdown SiGe HBTs in a BiCMOS technology

Having two, or more, transistors with different values of fT and BVCEO provides flexibility to circuit designers in making tradeoffs of power and performance. The process complexity and resulting cost of fabricating these transistors on the same wafer is another important factor. Three different approaches for co-integrating high-performance and high-breakdown SiGe npn HBTs with minimal process deviation are presented herein. The work features a high-performance HBT with fT × BVCEO product of 500GHz-V and a high-breakdown HBT with over 430GHz-V integrated on the same wafer with one-mask deviation.

Linewidth control effects on MOSFET ESD robustness

This paper advances state-of-the-art design layout considerations for deep sub-micron (0.25 μm) advanced single and stacked MOSFETs by addressing linewidth control effects on MOSFET ESD robustness. Advanced failure analysis tools are used to demonstrate linewidth bias. ESD robustness as a function of gate-to-gate spacings is addressed for the first time.

A novel Ccb and Rb reduction technique for high-speed SiGe HBTs

In this paper, we discuss a novel technique to reduce base resistance (R_b) and collector-base capacitance (C_cb) for higher F_max in high-speed SiGe HBTs. In order to reduce C_cb, we first located the origins of the different components of C_cb through AC extraction. Then we utilized scanning capacitance measurements (SCM) to examine the shape of the collector-base depletion. We then propose a method to reduce the extrinsic C_cb, namely by using reticle enhancement techniques to print a blocking oxide layer to inhibit boron outdiffusion. An additional benefit was the reduction of R_b by reducing the base link resistance.

Investigation of HBT layout impact on f T doubler performance for 90nm SiGe HBTs

Peak fT of 660 GHz is reported for HBT fT doubler designs in IBM 90 nm SiGe BiCMOS technology 9HP. This high performance fT doubler utilizes a longer HBT for output stage compared to the input stage HBT (length ratio 2:1) resulting in improved transconductance and lower thermal resistance. The impact of HBT layout on the circuit performance and trade-off between thermal resistance and fT is also investigated. fT doubler circuit can be used as a single transistor in several circuit applications like A/D converters and broadband circuits where higher performance is desired.

SiGe HBTs in 90nm BiCMOS technology demonstrating 300GHz/420GHz f T /f MAX through reduced R b and C cb parasitics

Scaling both the fT and the fMAX of SiGe HBTs is quite challenging due to the opposing physical device requirements for improving these figures of merit. In this paper, millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. These processes when combined with a novel approach to address the collector-base capacitance are shown to produce high performance SiGe HBT devices which demonstrate operating frequencies of 300/420GHz fT/fMAX. This is the first report of 90nm SiGe BICMOS with an fMAX exceeding 400GHz.