Marwan H. Khater

Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology

This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Masons unilateral gain of 285 GHz. f/sub MAX/ extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12/spl times/2.5 /spl mu/m/sup 2/ have these characteristics at a linear current of 1.0 mA//spl mu/m (8.3 mA//spl mu/m/sup 2/). Smaller transistors (0.12/spl times/0.5 /spl mu/m/sup 2/) have an f/sub T/ of 180 GHz at 800 /spl mu/A current. The devices have a pinched base sheet resistance of 2.5 k/spl Omega//sq. and an open-base breakdown voltage BV/sub CEO/ of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f/sub T/ at small lateral dimensions.

SiGe HBTs with cut-off frequency of 350 GHz

This work reports on SiGe HBTs with f/sub T/ of 350 GHz. This is the highest reported f/sub T/ for any Si-based transistor as well as any bipolar transistor. Associated f/sub max/ is 170 GHz, and BV/sub CEO/ and BV/sub CBO/ are measured to be 1.4 V and 5.0 V, respectively. Also achieved was the simultaneous optimization of f/sub T/ and f/sub max/ resulting in 270 GHz and 260 GHz, with BV/sub CEO/ and BV/sub CBO/ of 1.6 V and 5.5 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f/sub T/ and f/sub max/ values are also discussed.

A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

SiGe HBT technology with f/sub max//f/sub T/=350/300 GHz and gate delay below 3.3 ps

This work reports on SiGe HBT technology with f/sub max/ and f/sub T/ of 350 GHz and 300 GHz, respectively, and a gate delay below 3.3 ps. This is the highest reported speed for any Si-based transistor in terms of combined performance of f/sub max/ and f/sub T/ both of which exhibit 300 GHz and above. Associated BV/sub CEO/ and BV/sub CBO/ are measured to be 1.7 V and 5.6 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f/sub max/ and f/sub T/ values are also discussed.

Monolithic Silicon Integration of Scaled Photonic Switch Fabrics, CMOS Logic, and Device Driver Circuits

We demonstrate 4 × 4 and 8 × 8 switch fabrics in multistage topologies based on 2 × 2 Mach-Zehnder interferometer switching elements. These fabrics are integrated onto a single chip with digital CMOS logic, device drivers, thermo-optic phase tuners, and electro-optic phase modulators using IBMs 90 nm silicon integrated nanophotonics technology. We show that the various switch-and-driver systems are capable of delivering nanosecond-scale reconfiguration times, low crosstalk, compact footprints, low power dissipations, and broad spectral bandwidths. Moreover, we validate the dynamic reconfigurability of the switch fabric changing the state of the fabric using time slots with sub-100-ns durations. We further verify the integrity of high-speed data transfers under such dynamic operation. This chip-scale switching system technology may provide a compelling solution to replace some routing functionality currently implemented as bandwidth- and power-limited electronic switch chips in high-performance computing systems.

Half-terahertz operation of SiGe HBTs

This letter presents the first demonstration of a silicon-germanium heterojunction bipolar transistor (SiGe HBT) capable of operation above the one-half terahertz (500 GHz) frequency. An extracted peak unity gain cutoff frequency (f/sub T/) of 510 GHz at 4.5 K was measured for a 0.12/spl times/1.0 /spl mu/m/sup 2/ SiGe HBT (352 GHz at 300 K) at a breakdown voltage BV/sub CEO/ of 1.36 V (1.47 V at 300 K), yielding an f/sub T//spl times/BV/sub CEO/ product of 693.6 GHz-V at 4.5 K (517.4 GHz-V at 300 K).

A 210-GHz f/sub T/ SiGe HBT with a non-self-aligned structure

A record 210-GHz f/sub T/ SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA//spl mu/m/sup 2/ is fabricated with a new nonself-aligned (NSA) structure based on 0.18 /spl mu/m technology. This NSA structure has a low-complexity emitter and extrinsic base process which reduces overall thermal cycle and minimizes transient enhanced diffusion. A low-power performance has been achieved which requires only 1 mA collector current to reach 200-GHz f/sub T/. The performance is a result of narrow base width and reduced parasitics in the device. Detailed comparison is made to a 120-GHz self-aligned production device.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

High-

Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C-600°C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length.

\kappa

The goal of achieving terahertz (THz) transistors within the silicon material system has generated significant recent interest. In this paper, we use operating temperature as an effective way of gaining a better understanding of the performance limits of SiGe HBTs and their ultimate capabilities for achieving THz speeds. Different approaches for vertical profile scaling and reduction of parasitics are addressed, and three prototype fourth-generation SiGe HBTs are compared and evaluated down to deep cryogenic temperatures, using both dc and ac measurements. A record peak fT/fmax of 463/618 GHz was achieved at 4.5 K using 130-nm lithography (309/343 GHz at 300 K), demonstrating the feasibility of reaching half-THz fT and fmax simultaneously in a silicon-based transistor. The BVCEO of this cooled SiGe HBT was 1.6 V at 4.5 K (BVCBO = 5.6 V), yielding a record fT times BVCEO product of 750 GHzldrV (510 GHzldrV at 300 K). These remarkable levels of transistor performance and the associated interesting device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. It is predicted in a new scaling roadmap that fT/fmax of room-temperature SiGe HBTs could potentially achieve 782/910 GHz at a BVCEO of 1.1 V at the 32-nm lithographic node.