R.A.B. Engelen

A numerical method for efficient failure modelling of three-dimensional bond pad structures

Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. This is caused by the following technology and business trends: (1) increasing miniaturization, (2) introduction of new materials, (3) shorter time-to-market, (4) increasing design complexity and decreasing design margins, (5) shortened development and qualification times, (5) gap between technology and fundamental knowledge development [1]. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [2]. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate development is performed [3]. The scope of this paper is on the development of numerical models that are able to predict the failure sensitivity of complex three-dimensional microelectronic components while taking into account the details at the local scale (i.e., the back-end structure) by means of a multi-scale method. The damage sensitivity is calculated by means of an enhanced version of the previously introduced area release energy (ARE) criterion. This enhancement results in an efficient and accurate prediction of the energy release rate (ERR) at a selected bimaterial interface in any location. Moreover, due to the two-scale approach, local details of the structure are readily taken into account. In order to evaluate the efficiency and accuracy of the proposed method, several two-dimensional and three-dimensional benchmarks will be simulated. Finally, the failure sensitivity of a three-dimensional back-end structure during a wire pull test is evaluated.

Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy

This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken

Delamination analysis of Cu/low-k technology subjected to chemical-mechanical polishing process conditions

The mechanical response at the interface between the silicon, low-k and copper layer of the wafer is simulated herein under the loading of the chemical-mechanical polishing (CMP). To identify the possible generation/propagation of the initial crack, the warpage induced by the thin-film fabrication process are considered, and applying pressure, status of slurry and the copper thickness are treated as the parameter in the simulation. Both the simulation and experimental results indicate that the large blanket wafer within high applying pressure would exhibit high stresses possible to delaminate the interface at the periphery of the wafer, and reducing the copper thickness can diminish the possibility of the delamination/failure of the low-k material.

An Experimental-Numerical Study of Metal Peel off in Cu/low-k Back-End Structures

Wire pull tests are generally conducted to assess the wire bonding quality. Using Cu/low-k technology, two failure modes are usually observed: Failure in the neck of the wire (neck break) and metal peel off (MPO). The objective of our study is to investigate the root cause of metal peel off by using a combined experimental and numerical approach. First, dedicated failure analyses are conducted to identify the failure locations. Scanning electron microscopy analysis for a large number of completely failed samples shows that the delaminated interface, after MPO has occurred, is always the interface on top of the third metal layer, near the centre of the stack. However, these inspections do not indicate where and when MPO initiated. To understand the initiation, incremental (non-destructive) wire pull tests are used. These samples have not failed completely, but may already show the initiating crack in either of the two possible regions. Combined with use of scanning acoustic tomography (SCAT) and focused ion beam (FIB) show that MPO initiates by delamination in the back-end structure at the interface on top of the third metal layer. Secondly, a 3D FEM model for a half bond pad with partial wire bond is used to simulate the wire pull test, in order to understand the failure mode. Analyses using stress as a failure index indicates, however, that the top interface is the most critical one. This does not match with the experimental observation. Therefore, an alternative, energy-based failure index is used, the so-called area release energy method (ARE). The ARE method approximately identifies the same critical interface as found from experiments. It is assumed that the presence of a stiff layer nearby a potential crack location restricts the elastic deformation upon release. This indicates that the initiation of a crack in the upper and lower interfaces results in the release of a lower amount of energy when compared to an interface in the centre, where the surrounding material constrains the release less. A 2D test model confirms this assumption

Prediction of the epoxy moulding compound aging effect on package reliability

Abstract Most semi-conductor devices are encapsulated by epoxy moulding compound (EMC) material. Even after curing at the prescribed temperature and time in accordance with the supplier’s curing specifications often the product is not yet 100% fully cured. As a consequence, the curing process of a product continues much longer, leading to curing effects of the EMC during the lifetime of the package. In this paper, the effect of EMC curing during lifetime on package reliability is investigated. The visco-elastic mechanical properties of two commercial EMC materials are measured as a function of aging time. The resulting data is used to construct material models that are used in FE calculations. Aging effects on critical semi-conductor failure modes die cracking, compound cracking, wedge break, and delamination are addressed. Die and compound crack risks are predicted by common stress analysis. The risk of wedge break occurrence is investigated by detailed 3D modeling of the actual wires in the package using a global–local approach. Conclusions on delamination risks are made based on a parameter sensitivity analysis using a 3D cohesive zones approach to predict transient delamination. The package reliability study shows that the effect of EMC aging affects relevant failure modes in different ways.

Multi-scale energy-based failure modeling of bond pad structures

Thermo-mechanical reliability issues have been identified as major bottlenecks in the development of future microelectronic components. This is caused by the following technology and business trends: (1) increasing miniaturisation, (2) introduction of new materials, (3) shorter time-to-market, (4) increasing design complexity and decreasing design margins, (5) shortened development and qualification times, (5) gap between technology and fundamental knowledge development. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [8]. However, bad mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back end structure when no appropriate development is performed. The scope of this paper is on the development of numerical models that are able to predict the failure sensitivity of complex three-dimensional multi-layered structures while taking into account the details at the local scale of the microelectronic components by means of a multi-scale method. The damage sensitivity is calculated by means of an enhanced version of the previously introduced area release energy (ARE) criterion. This enhancement results in an efficient and accurate prediction of the energy release rate (ERR) at a selected bimaterial interface in any location. Moreover, due to the two-scale approach local details of the structure are readily taken into account. In order to evaluate the efficiency and accuracy of the proposed method, several two-dimensional and three-dimensional benchmarks will be simulated. The paper focusses on the enhanced ARE method, including several two- and three-dimensional benchmarks.

Virtual prototyping for PPM-level failures in microelectronic packages

In this paper, the interaction between chip and package is investigated with the focus on low ppm-level failures. More specifically, the failure mode of inter-metal shorts is investigated, caused by either electrical discharges (ESD) or internal/external mechanical forces. It is demonstrated that forces induced by the filler particles in the molding compound can cause these shorts. Finite element simulations are performed in order to estimate the stress levels in the backend stack of the integrated circuit (IC). Nano-indentation experiments are performed to measure the hardness of different passivation materials. The simulation and indentation results are combined with estimations and measurements of the particle size distribution, flow modeling and statistical methods. As such, the ppm-level of the failures could be attributed to the low chance that a filler particle would land on the critical location. Measures to prevent these failures are to be found in the area of improved passivation materials and/or recipes in combination with other molding compounds. For successful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development.

Failure modelling in flexible electronics

The first part of this paper deals with the analysis of layer buckling and delamination of thin him multi-layer structures that are used in flexible display applications. To this end, 250 nm thick indium tin oxide (ITO) layers have been deposited on a 200 mum thick high temperature aromatic polyester substrate (Arylitetrade) with a 3 mum silica-acrylate hybrid hard coat (HC). Typical buckle morphologies are determined from two-point bending experiments, in which buckle widths and heights are measured after straightening of the sample. Finite element simulations have been performed to estimate the corresponding interface properties and compressive strains in the layers, and to illustrate the effect of sample straightening on the buckle geometry. The second part considers the fracture sensitivity analysis of an active matrix Thin Film Transistor (TFT) display containing 512 times 256 pixels, with a typical pixel dimension of 160 times 160 mum. Due to the large scale differences between the display and the TFT patterning a multi-scale modelling framework has been developed, which allows to include realistic material stacks and a detailed pixel geometry. The resulting patterning effect shows an anisotropic behaviour at both the pixel level and the global display level due to the multi-scale approach. Using the Area Release Energy (ARE) method an energy-based failure criterion has been utilised to analyse cohesive failure at several (critical) locations in the pixel geometry. Specifically, the sensitivity to tunnelling cracks in the dielectric layers is regarded, which have been experimentally observed in comparable TFT samples that are subjected to tension. This local failure analysis allows for the identification of critical regions within the pixel geometry, which strongly depend on the location.

Optimization of Cu Low-k bond pad designs to improve mechanical robustness using the Area Release Energy method

In the development of present and future CMOS-technologies (CMOS065 and beyond) for microelectronic components the combination of state-of-the-art modeling techniques and experimental testing is crucial and provides a challenge to address the thermo-mechanical reliability issues and the demand for shorter time-to-market by the industry. Nowadays these modeling techniques often involve the construction of very detailed Cu low-k IC structures, which is still very time-consuming and computationally demanding. This paper adresses an alternative modeling strategy that intends to gain fundamental insights and understanding of the mechanisms that have an impact on the thermo-mechanical reliability of a Cu low-k device. As an example the relation between the metal densities of the various layers in a typical Cu low-k IC bond pad structure and the area release energy (ARE) criterion has been investigated. The modeling and computational effort have been considerably limited by building a simplified two- dimensional bond pad model. This model is constructed such that it is well capable to reveal the impact on the thermo-mechanical reliability and such that it is still representative for the behaviour of advanced Cu low-k structures. When optimizing the bond pad towards lower ARE levels for better mechanical robustness the impact of the metal density within the BE layers is evident. Furthermore, it shows that the metal density in a single layer does not only affect the ARE level in that specific layer, but it also influences the ARE profile within the entire stack. Clearly, the presented modeling strategy is suitable to identify the design parameters that play an important role when optimizing the thermo-mechanical performance of advanced Cu low-k structures. In combination with experimental tests (e.g. industrial qualification tests, interface strength measurements, etc.) it may provide a robust tool to further improve and ensure the reliability of present and future IC bond pad structures.