R.B. Nubling

A 6-b, 4 GSa/s GaAs HBT ADC

A GaAs-AlGaAs heterojunction bipolar transistor (HBT) process was developed to meet the speed, gain, and yield requirements for analog-to-digital converters (ADCs). The HBT has current gain of over 100 and f/sub T/ and f/sub MAX/ of over 50 GHz. A 6-b, 4 GSa/s (4 giga-samples/s) ADC was designed and fabricated in this process. The ADC uses an analog folding architecture, includes an on-chip master-slave track-and-hold (T/H) circuit, and provides Gray-encoded digital outputs. The ADC achieves 5.6 effective bits at 4 GSa/s, a faster clock rate than any noninterleaved semiconductor ADC reported to date. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 b) of 1.8 GHz at 4 GSa/s, higher than any published ADC. The chip operates at up to 6.5 GSa/s. GaAs HBT ICs are especially prone to high operating temperatures. This led to reliability problems that were overcome by the use of a fast DC thermal simulator written for this project. A SPICE model for self-heating effects is also described. >

Thermal design and simulation of bipolar integrated circuits

Keeping device operating temperatures within reasonable limits is necessary for reliability of all ICs and important for achieving the expected performance for many ICs. GaAs heterojunction bipolar transistors (HBTs) offer high speed and good device matching characteristics that are attractive for many high-speed circuits, but they are more susceptible than other IC technologies to the unexpected generation of very high junction temperatures. The reasons for this tendency are discussed, and an HBT sample-and-hold (S/H) circuit that had device temperature rises of over 300 degrees C is described. To address this problem, a new thermal simulation tool called ThCalc was created. ThCalc calculates the temperature profile of an IC and runs fast enough to allow calculations on a whole chip. ThCalc was used to redesign the S/H IC to reduce the largest temperature rise by a factor of 2.7 with a minimal impact on circuit size. >

A high-speed, low-power divide-by-4 frequency divider implemented with AlInAs/GaInAs HBT's

The authors describe the first frequency divider demonstrated using AlInAs/GaInAs heterojunction bipolar transistors (HBTs). The divider (a static 1/4 divider circuit) operates up to a maximum frequency of 17.1 GHz, corresponding to a gate delay of 29 ps for a bilevel current-mode logic (CML) gate with a fan-out of 2, and a total power consumption of 67 mW (about 4.5 mW per equivalent NOR gate). These results demonstrate the potential of AlInAs/GaInAs HBTs for implementing low-power, high-speed integrated circuits.<<ETX>>

High-performance MOCVD-grown AlGaAs/GaAs heterojunction bipolar transistors with carbon-doped base

Excellent microwave performance is demonstrated by metalorganic chemical vapor deposition (MOCVD) grown AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with carbon-doped base. These devices achieve a current-gain cutoff frequency of 76 GHz and a maximum frequency of oscillation of 102 GHz. Varying the device structures allows the current gain to reach over 300 in structures with a base doping of 2*10/sup 19 /cm/sup -3/. A static divide-by-four divider implemented with C-doped base HBTs has been operated up to a frequency of 20.4 GHz. These results indicate the suitability of carbon doping for high-performance HBTs.<<ETX>>

AlGaAs/GaAs HBT IC's for high-speed lightwave transmission systems

The implementation of multigigabit-per-second optical communication systems requires many high-speed electronic circuit components that meet stringent performance requirements. Several important research prototype circuits for fiber-optic transmission, implemented in a baseline AlGaAs/GaAs HBT process, are discussed. These include a 20 Gb/s decision circuit, a 27 Gb/s 1:2 demultiplexer, a 30 GB/s 2:1 multiplexer, a 27 Gb/s 4:1 multiplexer, and a 11 Gb/s laser driver IC. >

High-speed 8:1 multiplexer and 1:8 demultiplexer implemented with AlGaAs/GaAs HBTs

An 8:1 multiplexer (MUX) and 1:8 demultiplexer (DMUX) implemented with AlGaAs/GaAs heterojunction bipolar transistors are described. The circuits were designed for lightwave communications, and were demonstrated to operate at data rates above 6 Gb/s. These are among the fastest 8-b MUX-DMUX circuits ever reported. Each contains about 600 transistors and consumes about 1.5 W. The pair provides features such as resettable timing, data framing, and clock recovery circuitry, and a built-in decision circuit on the DMUX. Emitter-coupled logic (ECL) compatible input/output (1/O) signals are available. The circuits were implemented with bi-level current mode logic (CML) and require a -5.2-V power supply and a +1-V bias for ECL compatibility. >

A 6-bit, 4 GSa/s ADC fabricated in a GaAs HBT process

A GaAs-AlGaAs Heterojunction Bipolar Transistor (HBT) process was developed to meet the speed, gain and yield requirements for Analog to Digital Converters (ADCs). A 6-bit, 4 GSa/s (4 giga-samples per second) ADC was designed and fabricated in this process. The standard HBT used has an emitter area of 1.4/spl times/3.0 /spl mu/m; it has current gain of over 70 at I/sub c/=1 mA and f/sub T/ and f/sub MAX/ of over 50 GHz at I/sub c/=4 mA. The process also includes Schottky diodes, thin-film NiCr resistors, MIM capacitors and three levels of metal interconnect. The ADC uses an analog folding architecture to reduce transistor count and power well below that of a straight 6-bit flash ADC. It includes an on-chip track-and-hold (T/H) circuit and Gray-encoded digital outputs for best immunity to dynamic errors. The ADCs measured differential nonlinearity is less than /spl plusmn/0.5 LSB and its integral nonlinearity is less than /spl plusmn/0.8 LSB. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 bits) of 2.4 GHz at 3 GSa/s and 1.8 GHz at 4 GSa/s, higher than any ADC published to date. The chip operates at up to 6.5 GSa/s, but linearity at that clock rate is much worse.

A high-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have f/sub t/ values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.<<ETX>>

A high-speed multimodulus HBT prescaler for frequency synthesizer applications

A high-speed variable modulus prescaler that divides the input clock frequency by 128 up to 255 with unit step increment has been implemented with heterojunction bipolar transistor (HBT) technology. A maximum operating frequency of 9.72 GHz with power consumption of 650 mW has been measured. The high-speed performance is attributed to the circuit design, which minimizes the critical path delay, and the intrinsic high-speed characteristics of HBT technology. The phase noise of the prescaler is important for frequency synthesizer applications. With 6.24-GHz input frequency, the phase noise was -110 dBc/Hz at 100-Hz offset frequency and -120 dBc at 1-kHz offset frequency. The noise floor decreases as the input frequency decreases. Phase noises of -125 dBc/Hz at 100-Hz offset and -135 dBc/Hz at 1-kHz offset were obtained for a 1.2-GHz input frequency. >

11.6-GHz 1:4 regenerating demultiplexer with bit-rotation control and 6.1-GHz auto-latching phase-aligner ICs using AlGaAs/GaAs HBT technology

The authors present an 11.6-GHz 1:4 regenerating demultiplexer (demux) and a 6.1-GHz phase aligner, implemented using high-current-gain baseline AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology. The demux features a hybrid tree/shift register-type architecture optimized for high-speed and low-power operation, and is the fastest demux with bit-rotation control ever reported. It consumes 1.4 W of power with a single -5 V supply, and has a phase margin of 270 degrees and differential input data sensitivity of 56 mV/sub p-p/ at 11.6 Gb/s. The phase aligner incorporates an auto-latching scheme which allows the data to be latched using a timing signal derived on-chip from the data, and is the fastest fully monolithic phase aligner ever reported. It dissipates 0.8 W of power with a single -5 V supply and has differential input data sensitivity of 60 mV/sub p-p/ at 6.1 Gb/s. >