J.J. Corcoran

A 1-GHz 6-bit ADC system

A two-rank GaAs sample-and-hold (S/H) chip and four 250-MHz silicon digitizers form a 1-GHz 6-b analog-to-digital converter (ADC) system. The two rank S/H architecture avoids dynamic errors inherent to interleaved ADCs; accuracy exceeds 5.2 effective bits, up to 1-GHz input frequency. Special attention is paid to avoiding GaAs slow transient errors.

A 6-b, 4 GSa/s GaAs HBT ADC

A GaAs-AlGaAs heterojunction bipolar transistor (HBT) process was developed to meet the speed, gain, and yield requirements for analog-to-digital converters (ADCs). The HBT has current gain of over 100 and f/sub T/ and f/sub MAX/ of over 50 GHz. A 6-b, 4 GSa/s (4 giga-samples/s) ADC was designed and fabricated in this process. The ADC uses an analog folding architecture, includes an on-chip master-slave track-and-hold (T/H) circuit, and provides Gray-encoded digital outputs. The ADC achieves 5.6 effective bits at 4 GSa/s, a faster clock rate than any noninterleaved semiconductor ADC reported to date. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 b) of 1.8 GHz at 4 GSa/s, higher than any published ADC. The chip operates at up to 6.5 GSa/s. GaAs HBT ICs are especially prone to high operating temperatures. This led to reliability problems that were overcome by the use of a fast DC thermal simulator written for this project. A SPICE model for self-heating effects is also described. >

Thermal design and simulation of bipolar integrated circuits

Keeping device operating temperatures within reasonable limits is necessary for reliability of all ICs and important for achieving the expected performance for many ICs. GaAs heterojunction bipolar transistors (HBTs) offer high speed and good device matching characteristics that are attractive for many high-speed circuits, but they are more susceptible than other IC technologies to the unexpected generation of very high junction temperatures. The reasons for this tendency are discussed, and an HBT sample-and-hold (S/H) circuit that had device temperature rises of over 300 degrees C is described. To address this problem, a new thermal simulation tool called ThCalc was created. ThCalc calculates the temperature profile of an IC and runs fast enough to allow calculations on a whole chip. ThCalc was used to redesign the S/H IC to reduce the largest temperature rise by a factor of 2.7 with a minimal impact on circuit size. >

A 6-bit, 4 GSa/s ADC fabricated in a GaAs HBT process

A GaAs-AlGaAs Heterojunction Bipolar Transistor (HBT) process was developed to meet the speed, gain and yield requirements for Analog to Digital Converters (ADCs). A 6-bit, 4 GSa/s (4 giga-samples per second) ADC was designed and fabricated in this process. The standard HBT used has an emitter area of 1.4/spl times/3.0 /spl mu/m; it has current gain of over 70 at I/sub c/=1 mA and f/sub T/ and f/sub MAX/ of over 50 GHz at I/sub c/=4 mA. The process also includes Schottky diodes, thin-film NiCr resistors, MIM capacitors and three levels of metal interconnect. The ADC uses an analog folding architecture to reduce transistor count and power well below that of a straight 6-bit flash ADC. It includes an on-chip track-and-hold (T/H) circuit and Gray-encoded digital outputs for best immunity to dynamic errors. The ADCs measured differential nonlinearity is less than /spl plusmn/0.5 LSB and its integral nonlinearity is less than /spl plusmn/0.8 LSB. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 bits) of 2.4 GHz at 3 GSa/s and 1.8 GHz at 4 GSa/s, higher than any ADC published to date. The chip operates at up to 6.5 GSa/s, but linearity at that clock rate is much worse.

A High-Resolution Error Plotter for Analog-to-Digital Converters

This paper describes an automatic error plotting system for analog-to-digital converters (ADCs) which measures the static errors of the device under test at every quantization band edge (QBE) and displays them in graphical form. A quantization band edge is defined as any ADC input voltage which produces two adjacent output codes, each with 50-percent probability. The error of the ADC is then defined as the difference between the actual and nominal values of a QBE. A feedback loop which seeks each QBE is central to the system. Sample plots show the ability of the system to display common types of ADC errors and to display error signatures that often point to specific ADC problems. Resolution, accuracy, and (to a large extent) speed of the system depend on the digital voltmeter chosen as a standard. In a typical case, a 2000 point plot can be made in two minutes with a resolution and accuracy exceeding the weight of the ADCs least significant bit by an order of magnitude.

A 1GHz 6b ADC system

A two-rank GaAs sample and hold chip and four 250MHz ADCs developed to form a 1GHz 6b ADC system will be discussed. The two rank architecture avoids dynamic errors inherent to interleaved ADCs: accuracy exceeds 5.2 effective bits up to 1GHz input frequency.

A 2Gs/s HBT sample and hold

The authors describe a Schottky-diode sample-and-hold (S/H) circuit fabricated in an AlGaAs-GaAs heterojunction bipolar transistor (HBT) process. The transistors exhibit an f/sub T/ of over 50 GHz. The S/H circuit operates at up to 2G samples/s, with distortion below-40 dBc up to and beyond the Nyquist input frequency of 1 GHz.<<ETX>>

A high precision component-tolerant A/D convertor

A pulse transformer is used to double and sum voltages in an A/D encoder that is based on the recursive algorithm V/SUB i+1/=V/SUB REF/-s|V/SUB i/|. As a result of isolating the transformer from the input signal d.c. component, independence of circuit zero drift is achieved. Resistor and V/SUB BE/ mismatch do not affect the encoder accuracy. Automatic zero and gain correction are employed to provide stable adjustment-free operation. A custom analog processor chip carrying both MOS and bipolar transistors was fabricated to implement the algorithm. The 12-bit resolution with a maximum encoder error of 250 /spl mu/V in a temperature range from 0-70/spl deg/C was achieved at 20-kHz sampling rate.

Heating effects on the accuracy of HBT voltage comparators

Voltage comparators implemented with GaAs/(GaAl)As heterojunction bipolar transistors (HBTs) were examined for dynamic hysteresis effects. Heating effects were identified as the major source of hysteresis. An approximate model is proposed to explain the measured data. Suggestions for analog-to-digital converter design are discussed.

Thermal simulation and design of a GaAs HBT sample and hold circuit

Methods which are used to predict and measure device temperatures within an IC are described, and their application to the design of an HBT (heterojunction bipolar transistor) sample and hold circuit (S/H) is discussed. A new thermal simulation tool called ThCalc is also described. ThCalc calculates the temperature profile of an IC and runs fast enough to allow calculations on a whole chip.<<ETX>>