Julien Ducoté

Roughening of porous SiCOH materials in fluorocarbon plasmas

Porous SiCOH materials integration for integrated circuits faces serious challenges such as roughening during the etch process. In this study, atomic force microscopy is used to investigate the kinetics of SiCOH materials roughening when they are etched in fluorocarbon plasmas. We show that the root mean square roughness and the correlation length linearly increase with the etched depth, after an initiation period. We propose that: (1) during the first few seconds of the etch process, the surface of porous SiCOH materials gets denser. (2) Cracks are formed, leading to the formation of deep and narrow pits. (3) Plasma radicals diffuse through those pits and the pore network and modify the porous material at the bottom of the pits. (4) The difference in material density and composition between the surface and the bottom of the pits leads to a difference in etch rate and an amplification of the roughness. In addition to this intrinsic roughening mechanism, the presence of a metallic mask (titanium nitride) c...

Target design optimization for overlay scatterometry to improve on-product overlay

Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow added functionality to existing marks within the current mark area, such as monitoring process asymmetry or multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning. With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window is enhanced, while improved on-product overlay performance is obtained.

Patterning critical dimension control for advanced logic nodes

Abstract. Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.

Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration.

One of the main process control challenges in logic process integration is the contact to gate overlay. Usual ways for overlay control are run to run corrections (high order process corrections) and scanner control (baseliner control loop) to keep overlay within the very tight ITRS specifications, i.e. 7nm mean+3sigma. It is known that process integration can lead to specific overlay distortion (CMP, thermal treatment etc…) which are usually partly handled by high order process corrections at scanner level. In addition, recently we have shown that etch process can also lead to local overlay distortions, especially at the wafer edge [1]. In this paper we look into another overlay distortion level which can happen during etch processes. We will show that resist cure steps during gate patterning affect lithography defined profiles leading to local pattern shifting. This so called gate shifting has been characterized by etch process partitioning during a typical high-K metal gate patterning with spinon carbon and Si-ARC lithography stack onto a high-K metal gate / poly-silicon / oxide hard mask stack. We will show that modifying the resist-cure / Si-ARC open chemistry strongly contributes to gate shifting reduction by an equivalent of 40% overlay margin reduction.

Etching process scalability and challenges for ULK materials

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.

SEM contour based metrology for microlens process studies in CMOS image sensor technologies

From the first digital cameras which appeared during the 70s to cameras of current smartphones, image sensors have undergone significant technological development in the last decades. The development of CMOS image sensor technologies in the 90s has been the main driver of the recent progresses. The main component of an image sensor is the pixel. A pixel contains a photodiode connected to transistors but only the photodiode area is light sensitive. This results in a significant loss of efficiency. To solve this issue, microlenses are used to focus the incident light on the photodiode. A microlens array is made out of a transparent material and has a spherical cap shape. To obtain this spherical shape, a lithography process is performed to generate resist blocks which are then annealed above their glass transition temperature (reflow). Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product. The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.

Microlens under melt in-line monitoring based on application of neural network automatic defect classification

The usage of convolutional neural networks (CNN) on images is spreading into various topics in lot of industries. Today in the semiconductor industry CNN are used to perform Automatic Defect Classification (ADC) on SEM review images in almost real time and with level of success as high as trained operators can do or more [1,2]. The possibilities to get new kind of information from images offer to engineers multiple potential usages. In this paper we propose to present derivatives usages of CNN applied to the CD-SEM metrology with specific focus on an application to detect undermelted microlens in our imager process flow [3]. CD-SEM metrology is used to perform Critical Dimension (CD) measurement on almost all patterning steps in the wafer cycle (after lithography and after etch). CNN allows us to get more information from pictures than only dimensions measured by the CD-SEM used to feed a control card. In our imager process flow we have steps to form microlenses. The microlens process fabrication consists in a first lithography step where microlens matrix is defined in resist. The result is a matrix of quite square parallelepipoid microlenses followed by a melting step in order to reflow resists and eventually form microlens with spherical cap shape. The figure 1 shows the evolution of microlens shape in function of melting process time.

Robust 2D patterns process variability assessment using CD-SEM contour extraction offline metrology

Today’s CD-SEM metrology is challenged when it comes to measuring complex features found in patterning hotspots (like tip to tip, tip to side, necking and bridging). Metrology analysis tools allow us to extract SEM contours of a feature and convert them into a GDS format from which dimensional data can be extracted. While the CD-SEM is being used to take images, the actual measurement and the choice of what needs to be measured is done offline. Most of the time this method is used for OPC model creation but barely for process variability analysis at nominal process conditions. We showed in a previous paper [1] that it is possible to study lithography to etch transfer behavior of a hotspot using SEM contours. The goal of the current paper is to go extend this methodology to quantify process variability of 2D features using a new tooling to measure contour data.

Advanced metrology by offline SEM data processing

Today’s technology nodes contain more and more complex designs bringing increasing challenges to chip manufacturing process steps. It is necessary to have an efficient metrology to assess process variability of these complex patterns and thus extract relevant data to generate process aware design rules and to improve OPC models. Today process variability is mostly addressed through the analysis of in-line monitoring features which are often designed to support robust measurements and as a consequence are not always very representative of critical design rules. CD-SEM is the main CD metrology technique used in chip manufacturing process but it is challenged when it comes to measure metrics like tip to tip, tip to line, areas or necking in high quantity and with robustness. CD-SEM images contain a lot of information that is not always used in metrology. Suppliers have provided tools that allow engineers to extract the SEM contours of their features and to convert them into a GDS. Contours can be seen as the signature of the shape as it contains all the dimensional data. Thus the methodology is to use the CD-SEM to take high quality images then generate SEM contours and create a data base out of them. Contours are used to feed an offline metrology tool that will process them to extract different metrics. It was shown in two previous papers that it is possible to perform complex measurements on hotspots at different process steps (lithography, etch, copper CMP) by using SEM contours with an in-house offline metrology tool. In the current paper, the methodology presented previously will be expanded to improve its robustness and combined with the use of phylogeny to classify the SEM images according to their geometrical proximities.

64nm pitch metal1 double patterning metrology: CD and OVL control by SEMCD, image based overlay and diffraction based overlay

Patterning process control of advanced nodes has required major changes over the last few years. Process control needs of critical patterning levels since 28nm technology node is extremely aggressive showing that metrology accuracy/sensitivity must be finely tuned. The introduction of pitch splitting (Litho-Etch-Litho-Etch) at 14FDSOInm node requires the development of specific metrologies to adopt advanced process control (for CD, overlay and focus corrections). The pitch splitting process leads to final line CD uniformities that are a combination of the CD uniformities of the two exposures, while the space CD uniformities are depending on both CD and OVL variability. In this paper, investigations of CD and OVL process control of 64nm minimum pitch at Metal1 level of 14FDSOI technology, within the double patterning process flow (Litho, hard mask etch, line etch) are presented. Various measurements with SEMCD tools (Hitachi), and overlay tools (KT for Image Based Overlay – IBO, and ASML for Diffraction Based Overlay – DBO) are compared. Metrology targets are embedded within a block instanced several times within the field to perform intra-field process variations characterizations. Specific SEMCD targets were designed for independent measurement of both line CD (A and B) and space CD (A to B and B to A) for each exposure within a single measurement during the DP flow. Based on those measurements correlation between overlay determined with SEMCD and with standard overlay tools can be evaluated. Such correlation at different steps through the DP flow is investigated regarding the metrology type. Process correction models are evaluated with respect to the measurement type and the intra-field sampling.