R. Cellier

A 0.01%THD, 70dB PSRR Single Ended Class D using variable hysteresis control for headphone amplifiers

Switching audio amplifiers are widely used in HBridge topology thanks to their high efficiency; however low audio performances in single ended power stage topology is a strong weakness leading to not be used for headset applications. This paper explains the importance of efficient error correction in Single Ended Class-D audio amplifier. A hysteresis control for Class-D amplifier with a variable window is also presented. The analyses are verified by simulations and measurements. The proposed solution was fabricated in 0.13µm CMOS technology with an active area of 0.2mm2. It could be used in single ended output configuration fully compatible with common headset connectors. The proposed Class-D amplifier achieves a harmonic distortion of 0.01% and a power supply rejection of 70dB with a quite low static current consumption.

A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time

This paper presents a continuous-time third-order ΣΔ modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed ΣΔ modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-to-noise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering.

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In this paper, a time-integration based passive quenching - active recharge circuit for Geiger-mode avalanche diodes has been proposed with the aim of minimizing the avalanche charge and providing a hold-off time tunable within wide range. These are indeed important features to be taken into account in the design of the avalanche diode quenching - reset electronics. Furthermore a hold-off time tunable within a wide range is typically desirable in every application where a full characterization of the device dark count rate is required. A correct operation of the proposed circuit, designed in a commercial High-Voltage CMOS 0.35um technology, is assessed through circuit simulations as well as Monte Carlo analysis in the Cadence Environment.

ADC for a Digital Closed-Loop Class-D Amplifier

This work describes the development of a novel position sensitive charged particle detector suitable for nuclear physics applications, in the field of High Energy Physics experiments and emerging medical applications such as hadrontherapy and Proton Computed Tomography (pCT). The “3D Silicon Coincidence Avalanche Detector” (3D-SiCAD) pixel consists of a pair of 3D vertically aligned Geiger-mode avalanche diodes (SPAD) working in time-coincidence mode. This novel detector features single charged particle detection capability, compatibility with both standard CMOS technology and commercially available 3D integration techniques, and very low noise. In order to demonstrate this latter point, a first 3D-SiCAD prototype has been designed and fabricated using a standard CMOS technology and a 3D assembly technique based on gold micro-bumps. In a first phase, preliminary measurements over two adjacent “in-plane” avalanche diodes operated in coincidence-mode have demonstrated a very high noise rejection capability, up to 3-4 orders of magnitude lower than the intrinsic dark count rate of each SPAD cell. Afterwards, measurements on a real 3D pixel have been carried out, obtaining however noise rejection capabilities lower than expected. Optical cross-talk occurring between the two sensing level of the 3D-SiCAD pixel has been found to be the phenomenon responsible for this underperformance. Nevertheless this limitation can be easily overcome by interposing a fully absorbing/reflecting material between the two sensing levels. These first results are very encouraging for the realization of a fully CMOS integrated 3D-SiCAD detector, targeting application requiring high-precision tracking, ultra-fast response times and very low noise.

A time-integration based quenching circuit for Geiger-mode avalanche diodes

This paper presents a continuous-time 3^rd order ΣΔ modulator implemented in 40-nm CMOS technology for closing the feedback loop of a digital class-D audio amplifier. The proposed ΣΔ A/D converter consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB DR and 72-dB peak SNDR. The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees 3^rd order anti-aliasing filtering.

Development of a 3D silicon coincidence avalanche detector for charged particle tracking in medical applications

In this paper, we describe a valley-switching self-calibration strategy, which permits to minimize commutation loss in Flyback active-clamp converters working in valley switching mode. This strategy allows an optimal behavior of the converter commutation regardless of its parasitic drain-source capacitance behavior. This strategy can be applied on wide input voltage range Flyback active-clamp converters, in which the soft switching cannot be maintained on the whole working range. Our strategy has been tested on a 17 V to 130 V input voltage converter with a 12 V-40W output. Efficiency increases up to 2% at high input voltages compared to standard converter control strategy.

A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier

This article presents a modified control strategy for a large input voltage range in an active-clamp soft switching converter. This control strategy is based on frequency modulation and allows a soft switching of all semiconductor devices on a large input voltage range. This frequency modulation also minimizes transformer loss without losing soft switching both on primary and secondary side of the converter. The proposed control strategy was implemented on a 30W prototype with a switching frequency up to 215kHz. The prototype is soft switching on an input voltage range between 15V and 75V, confirming the benefits of the presented control strategy with efficiency above 90% on a 28-63V range.

Self-calibrated valley switching for wide range Flyback active-clamp DC-DC converter

The goal of this paper is to provide some useful design guidelines at the device level regarding the main challenges to be typically faced in the design and integration of Geiger-mode avalanche diodes in a standard CMOS process. Different techniques are found in literature in order to avoid premature edge breakdown with the aim of limiting the electric field at the edges to be weaker than in the multiplication region. In this article, the use of such techniques, the conditions where they can effectively work and above all their limitations are studied by means of TCAD simulations for various diode architectures. Additionally, the noise performance is discussed by focusing on the band-to-band tunneling and shallow trench isolation enhanced dark count rates. Geiger-mode bias techniques as well as a synthesis on the pros and cons of the various avalanche diode architectures are finally presented aiming at facilitating future design choices.

Control optimization of a dual resonant converter for 15–75V input voltage application

In this paper a preliminary study of coincidence Avalanche Pixel Sensors (APiX) for High Energy Physics (HEP) applications is presented. In this preliminary work, some PEB prevention techniques found in literature have been studied by TCAD simulations adopting 2D Cylindrical geometrical models and 130nm CMOS process technological data.