R. Coquand

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced ION gain as high as +40% at LG = 45 nm is achieved for a multiple-NW active pattern.

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various RRAM based neuromorphic circuits were proposed and investigated, using planar devices.

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H2 annealing used for Ω-Gate. On short gate length, a strain-induced Ion gain as high as 40% at LG=45nm is achieved for multiple-NWs active pattern.

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs

We report an experimental study of the carrier transport in long channel tri-gate (TG) and omega-gate (ΩG) Si nanowire (NW) transistors with cross-section width down to 10 nm. Electron and hole mobility have been measured down to 20 K. We discuss the influence of channel shape, channel width and strain on carrier mobility. In particular we have shown that transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and ΩGNWs. We have also demonstrated the effectiveness of an additional uniaxial strain in NWs down to 10nm width.

300 K operating full-CMOS integrated Single Electron Transistor (SET)-FET circuits

We demonstrate the first Single Electron Transistor (SET) with high-k/metal gate operating at room temperature (at VD=0.9 V) cointegrated with fully depleted SOI (FDSOI) MOSFET (with 20 nm gate length) to realize a hybrid SET-FET circuit. Our resulting circuit exhibits typical SET oscillations upto record milliampere range. We also demonstrate a SET-FET based Negative Differential Resistance (NDR) device with 104 peak-valley-current-ratio and also a literal gate for multivalued logic applications.

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for LG=20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing to periodically peaked ID-VGs. This transition is brought about by process induced channel potential variability (due to disorder) in nanowires and poses a challenge to further scaling. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD=±0.9 V!) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of beyond Moore devices.

Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives

In this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then 2 potential applications are discussed using design approach. For high density, the Vertical RRAM cell features and circuit are dimensioned to optimize the memory page density. Finally, for neuromorphic applications, selector and array configuration are tuned to reduce the variability in terms of voltage seen by each cell constituting a vertical synapse.

Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs

Low-frequency noise (LFN) has been investigated in tri-gate (TG) Si nanowire (NW) FET. We have carefully measured and analyzed LFN for gate length down to 40 nm and cross-section width down to 10 nm. Drain current noise spectral density has been measured in linear region from weak to strong inversion of transistor operation. In particular, we have shown that the LFN behavior is in good agreement with carrier number fluctuations with correlated mobility fluctuations model in ultra-scaled TGNW FETs. We did not observe large contribution due to surface orientation difference between (100) top and (110) side-wall surfaces of TGNW. Moreover, the extracted oxide trap density is roughly the same for reference wide devices and TGNW FETs without significant impact of channel area downscaling and geometry.

Influence of technological and geometrical parameters on low-frequency noise in SOI omega-gate nanowire NMOSFETs

A study of the interface quality in ultra-scaled omega-gate nanowire NMOSFETs, with variant technological boosters, is presented by low-frequency noise (LFN) measurements. Excellent quality of the interfaces has been achieved down to narrow width (10nm), and whatever the technological splits. In particular, efficient tensile stressor has been demonstrated with high performance enhancement and preserved noise performance fulfilling the ITRS 1/f LFN road map.

FDSOI nanowires: An opportunity for hybrid circuit with field effect and single electron transistors

Thanks to a well-controlled CMOS FDSOI technology we have recently been able to demonstrate breakthroughs in the combined use of field effect and Coulomb blockade phenomena. On one hand, we have demonstrated room temperaturehybrid circuits based on single electron transistors and MOSFETs. On the other hand, we have shown the practical performance of electron pumps designed with a single silicided Coulomb island and MOSFETs as tunable barriers for metrologic applications.