S. Monfray

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-/spl mu/m PMOS devices showing substantial efficiency in reducing SCE and I/sub OFF/ current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation

In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m and I/sub off/=0.8 /spl mu/A//spl mu/m and demonstrate that the FET principle is still confirmed at room temperature. We have deliberately used a non-overlapped SD/gate architecture, showing that, with adapted channel doping, it not only performs equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable. Finally, we show that quantization of energy in the channel motivates a study of performance at low temperature, and that the leading effect at low temperature and low voltage is Coulomb blockade.

Silicon-on-nothing MOSFETs: performance, short-channel effects, and backgate coupling

Silicon-on-nothing (SON) transistors with gate length varying from 0.25 /spl mu/m down to 80 nm exhibit excellent performance and scalability. The silicon-on-insulator (SOI)-like architecture with thin fully depleted Si film and ultrathin buried oxide results in attenuated short-channel effects (charge sharing, DIBL and fringing fields), high current, and electron mobility. A new model accounts for the intrinsic mechanisms of operation in SON MOSFETs: i) substrate depletion governed by source and drain via doping modulation, ii) relatively low coupling between the front- and backgates, iii) role of ultrathin buried oxide. The proposed model reproduces the variations of the threshold voltage and subthreshold swing and is useful for further device optimization.

Highly performant double gate MOSFET realized with SON process

Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and low power) with very high Ion/Ioff trade off. Drive currents of 1954 /spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333 /spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained at 1.2 V with Tox = 20 /spl Aring/ and Lgate = 70 nm. DIBL is very well controlled, measured below 60 mV for gates as short as 40 nm. These features place our devices among the most performant ever reported.

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced ION gain as high as +40% at LG = 45 nm is achieved for a multiple-NW active pattern.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V<inf>bb</inf>) enables V<inf>t</inf> modulation of more than 125mV with a V<inf>bb</inf> of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V<inf>t</inf> and power management applications. We explore the impact of GP, BOX thickness and V<inf>bb</inf> on local V<inf>t</inf> variability for the first time. Excellent A<inf>Vt</inf> of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I<inf>g</inf>) and lower external resistance (R<inf>ext</inf>), thanks to a thicker inversion gate dielectric (T<inf>inv</inf>) and body (T<inf>si</inf>) thickness.

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

In this paper, the first SON (Silicon On Nothing) devices with metal gate are presented. Extremely thin fully depleted Si-films are recognized to be integrable with single-metal gate (mid-gap) due to their intrinsically low threshold voltage. In this work we present mid-gap CoSi/sub 2/ metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Due to its architecture and to the continuity between SD areas and the bulk, SON transistors allow deep silicidation processing down to the gate oxide, meaning that no more polysilicon is left. SON PMOS devices were performed with 55 nm CoSi/sub 2/ gate length with 5 nm of Si-channel thickness, and show excellent performances (350 /spl mu/A//spl mu/m I/sub on/ with only 0.1 nA I/sub off/ at -1.4 V with T/sub ox/=20 /spl Aring/). The polydepletion is of course suppressed and the gate resistance (<2 /spl Omega///spl square/) is very competitive for RF applications.

Semi-flexible bimetal-based thermal energy harvesters

This paper introduces a new semi-flexible device able to turn thermal gradients into electricity by using a curved bimetal coupled to an electret-based converter. In fact, a two-step conversion is carried out: (i) a curved bimetal turns the thermal gradient into a mechanical oscillation that is then (ii) converted into electricity thanks to an electrostatic converter using electrets in Teflon?. The semi-flexible and low-cost design of these new energy converters pave the way to mass production over large areas of thermal energy harvesters. Raw output powers up to 13.46??W per device were reached on a hot source at 60??C?with forced convection. Then, a DC-to-DC flyback converter has been sized to turn the energy harvesters? raw output powers into a viable supply source for an electronic circuit (DC@3?V). At the end, 10??W of directly usable output power were reached with 3 devices, which is compatible with wireless sensor network powering applications.

On the Limitations of Silicon for I-MOS Integration

This paper discusses the scalability of the supply voltage with the device length in silicon impact ionization MOS (I-MOS) transistors, by presenting results from both experiments and simulations. It is first shown that the supply voltage of silicon I-MOS devices saturates at low device lengths and does not fall under about 4.5 V. Second, it is shown from 2-D simulations and measurements on sub-100-nm devices that the transistor effect is lost also at low device lengths. We then propose an explanation for this phenomenon, based once again on the saturation of the supply voltage. Based on our findings, we conclude that silicon may be an inadequate material for I-MOS devices, and we envision germanium as a more promising replacement.

Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates

In this paper we compare two innovative approaches to the integration of Ge-channel on Insulator MOSFETs from conventional Bulk-Si substrates. The first one is based on the Ge-condensation process, and the second one relies on the epitaxy of a pure ultra-thin 2.3 nm-thick Ge layer performed directly on Si. With the second approach, we demonstrate for the first time highly-performant Localized GeOI pMOS devices down to 75 nm gate length, with controlled threshold voltage and drive current up to 600 muA/m@-1.1 V. We show a +35% improvement in drive current compared to Si references for the same Gate overdrive.