R. de Werdt

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

The authors describe a 25.2 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 0.5 mu m at a comparatively relaxed 1.2 mu m pitch. A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area. The functionality of the cell was shown on a 1 kb test memory.<<ETX>>

Drift of the breakdown voltage in p-n junctions in silicon (walk-out)

Abstract A quantitative model for the time behaviour of the walk-out phenomenon in planar p - n junctions is given. The injection of hot carriers into SiO 2 and subsequent trapping of part of them is assumed to be the origin of the walk-out. The model is found to be in reasonable agreement with the experimental results on both p + − n and n + − p junctions. The parameters in the model are discussed in relation with the experiments.

Combination of field and current access magnetic bubble circuits

A high-frequency current-access output gate is applied to a field-access memory operating at lower frequencies. This takes advantage of materials whose maximum velocity is not reached at the obtainable rotating-field frequency. The access and cycle times can decrease easily by a factor of 2 to 6. A number of elements has been designed, necessary to perform a combination of field-access and current-access circuits. Conductor propagation structures and field-current transfer gates have been tested on high mobility 7μm-bubble La, Ga-YIG. These elements, though not optimised, already have overlapping margins. Single-mask conductors consisting entirely of permalloy or a sandwich of permalloy on gold both propagate bubbles up to about 1 MHz frequency.

Profile engineering for sub-micron CMOS using high energy ion implantation

An improved implantation scheme has been developed for a submicron retrograde twin-well CMOS (complementary metal-oxide-semiconductor) process. A blanket p-well implantation is used to avoid one photoresist step. The use of a phosphorus compensating implantation for PMOS (p-channel MOS) transistor threshold voltage control avoids another resist step and photoresist processing on gate oxide. The latter results in an improved gate oxide integrity. The new implantation scheme has been successfully employed in the fabrication of a 1-Mb SRAM (static random-access memory) on 150-mm wafers.<<ETX>>

Geometry Dependent Bird's Beak Formation for Submicron LOCOS Isolation

Birds beak formation is one of the major problems for LOCOS field isolation. In this paper we demonstrate that the birds beak length is not a constant, but depends strongly on geometry of the oxidatioin mask for submicron mask dimensions. The birds beak length can vary up to a factor of 4, dependent on mask geometry. Four independent geometry effects are distinguished and their impact on an IC-process is discussed.

Electrical Characterization of a Submicron Titanium Silicide Local Interconnect Technology

In advanced CMOS technologies the use of a local interconnect technology, under the intermediate oxide provides a means of increasing circuit packing density at the cost of only one additional mask layer. A scheme involving the creation of titanium silicide interconnect has been incorporated in a submicron CMOS technology used for the production of 1 Mbit static RAMs. This paper describes the full electrical characterisation of this local interconnect technology as it is used in this process. It is shown that the titanium/amorphous silicon thickness ratio must be less than 0.38 if silicon suckout from the active area regions is to be avoided. Suckout of silicon may result in increased junction leakage dependent on the silicide strap layout. An increase in the p-channel transistor series resistance may also occur.

Improved propagation, stretching and annihilation of magnetic bubbles in current‐access devices

New functional elements have been tested for 16 μm‐period current‐access circuits in single and double mask structures. Improved propagate patterns exhibit 15% operating margins at 1 MHz frequency and 20 mA current. Heat dissipation drops to 0.3 mW per conductor period. In conventional CaGe‐garnet films it has been possible to increase the maximum frequency to 1.9 MHz at 60 mA. In the first orthorhombic films to be processed, 4 MHz has been reached already at 20 mA current. High‐frequency current‐access stretching of bubbles prior to detection is discussed. Operating margins of 10% are obtained up to 700 kHz in a pattern that stretches bubbles normal to their propagation direction. High‐frequency writing is obtained by combining a number of field‐access generators with an annihilator in the conductor track. A compact current‐field‐access swap gate allows the closest possible packing of the field‐access minor loops. These elements have not yet been combined for the same conductor structure. In principle, h...

Conductor and transfer‐gate performance of single‐mask field‐current access magnetic‐bubble devices

Bubble propagation has been investigated in conductor structures on 5 μm bubble (Y,Sm,Lu,Ca)3(Fe,Ge)5O12. The conductors consist either entirely of Permalloy or of a sandwich of Permalloy on gold. A static in‐plane field is used for unidirectional bubble propagation. The dependence of bubble motion on current amplitude and in‐plane field magnitude has been measured at low and high frequencies. The bubble motion was observed to consist of a first slow step where the current acts against the in‐plane field, and a second quick step where both act together. Attainable frequencies increase with increasing in‐plane field and current intensities up to a maximum of 1.1 MHz. The sandwich conductor has a 12% operating margin at 830 kHz frequency and 30 mA current. It performs better than the all‐Permalloy conductor at the same overall spacing of the Permalloy to the epifilm. An improved transfer gate from current to field‐access has an 18% margin, from field to current‐access 16%, at 100 kHz. The overlap with the c...

A double level metallization system having 2 mu m pitch for both levels

A double-layer metal (DLM) process having 2- mu m pitch for both metal levels has been successfully developed. This DLM system has been used in a 0.7- mu m CMOS process to fabricate 1-M SRAM and 256 K SRAM devices. Some relevant design rules are 1- mu m metal line and space for both levels, and 0.9- mu m contact and via openings. To meet these requirements, the process features planarization to minimize topology at LOCOS, polysilicon, and metal levels. The technological results are presented as well as reliability and electrical results. Photographs of fully processed and functional 256 K and 1-M high-performance SRAMs are shown.<<ETX>>

A 1M SRAM with full CMOS cells fabricated in a 0.7&#181;m technology

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.