Andre Stolmeijer

Profile engineering for sub-micron CMOS using high energy ion implantation

An improved implantation scheme has been developed for a submicron retrograde twin-well CMOS (complementary metal-oxide-semiconductor) process. A blanket p-well implantation is used to avoid one photoresist step. The use of a phosphorus compensating implantation for PMOS (p-channel MOS) transistor threshold voltage control avoids another resist step and photoresist processing on gate oxide. The latter results in an improved gate oxide integrity. The new implantation scheme has been successfully employed in the fabrication of a 1-Mb SRAM (static random-access memory) on 150-mm wafers.<<ETX>>

The use of TiSi/sub 2/ local interconnect as an effective contact etch barrier

TiSi/sub 2/ local interconnect was used as an overetch barrier layer for shallow submicron contacts in a fully planarized submicron salicide CMOS process used for manufacturing 1-Mb SRAMs. By placing a pad of local interconnect under all contacts to polysilicon, the complete removal of the silicide is prevented. The result is a stable, low contact resistance to polysilicon.<<ETX>>

A 1M SRAM with full CMOS cells fabricated in a 0.7&#181;m technology

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.