H.G. Pomp

Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's

Hot-carrier degradation is mainly caused by negative oxide-charge generation in the present-day PMOSFETs. We present experimental evidence showing that two more degradation mechanisms are important in the case of deep-submicron PMOSFETs. Firstly, the generation of interface states is significant in the case of sub-half-micron PMOSFETs. It even limits the lifetime of surface-channel transistors. Secondly, the generation of positive oxide charge by holes influences the characteristics. The latter process has been established unambiguously for the first time in PMOSFETs. We measured the bias dependence, the length dependence, and the time dependence separately for all three microscopic degradation mechanisms. We calculated the influence of these three mechanisms on the transconductance degradation. Summation of the three effects yields an excellent description of the experimentally determined time dependence of PMOSFET degradation for many bias conditions and various transistor geometries with either nitrided or conventional gate oxide. >

Shallow boron junctions and preamorphization for deep submicron silicon technology

In this study, shallow p+‐n junction diodes were formed by implanting BF+2 ions into single‐crystal silicon or silicon preamorphized by either Si or Ge implantation. BF+2 implantation at energies of 20 or 25 keV and a dose of 1×1015 cm−2 was followed by furnace annealing at 600 °C in nitrogen ambient. Most samples received a further nitrogen‐ambient anneal at 850 °C, with various periods of time. Secondary ion mass spectroscopy was used to measure the B profiles. Cross‐sectional transmission electron microscopy was used to study the amorphous layers and the defects remaining after annealing. Electrical characterization of the diodes is described. In preamorphized samples, the residual defect density decreases, and the defect band located at the original amorphous‐crystalline interface becomes sharper, as the mass of the amorphizing ion species is increased. Ideal low‐leakage shallow junctions can be made following either Si or Ge preamorphization and furnace annealing, without removing all the defects ind...

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

The authors describe a 25.2 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 0.5 mu m at a comparatively relaxed 1.2 mu m pitch. A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area. The functionality of the cell was shown on a 1 kb test memory.<<ETX>>

N/sub 2/O nitrided gate dielectric technology for 0.25 mu m CMOS

A technology for thin N/sub 2/O nitrided gate oxide was developed for 0.25 mu m CMOS. A gate dielectric of 7.5 nm thickness was grown using a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900 degrees C, the second step is nitridation in pure N/sub 2/O at 950 degrees C. The use of lightly nitrided gate dielectrics improved the gate oxide quality and did not degrade the MOS device properties. Furthermore, boron diffusion through the thin dielectric of BF/sub 2/ doped poly gates was suppressed by N/sub 2/O nitridation.<<ETX>>

Lightly nitrided gate oxides for 0.25 mm CMOS

Abstract A N 2 O lightly nitrided gate dielectric technology is developed for 0.25 μm CMOS. Gate dielectric with a thickness of 7.5 nm is grown in a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900° C , the second step is nitridation in pure N 2 O at 950° C . The use of lightly nitrided gate dielectrics improves the gate oxide quality and has no adverse effects on devices. Furthermore boron diffusion through thin gate oxide of BF + 2 doped poly gates is suppressed. This makes it possible to use low energy BF + 2 implants for shallow drain formation. The physical and electrical characterisation of MOS capacitors and 0.25 μm transistors will be presented.

New hot-carrier degradation mechanisms in 0.25 /spl mu/m PMOSFETs

PMOSFET hot-carrier reliability is often proposed to he limited by negative oxide charge. We show that interface states determine the lifetime in deep submicron PMOSFETs. Clear evidence for additional positive oxide-charge generation is presented for the first time. The bias-length and time dependences are measured for all three degradation mechanisms. Combining these three mechanism describes the time dependence of PMOSFET degradation convincingly for many geometries at many bias conditions.<<ETX>>

The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors

An experimental study of hot carrier degradation and power supply voltage scaling of deep-submicron NMOS devices is presented. Devices were optimized for processes with design rule between 2 mu m and 0.17 mu m. Charge pumping measurements showed that the lifetime based on interface state generation in the devices was determined only by I/sub sub//I/sub d/ and the drain current. It did not depend on gate length, oxide thickness, and substrate doping. The lifetime (determined by shifts in the maximum linear transconductance) of the devices with minimum gate length of different processes fall on a single life in plots of tau *I/sub d/ versus I/sub sub//I/sub d/. This behavior can be explained by the impact of interface damage on the transistor parameters of these devices. Light emission spectra and device simulation showed that nonlocal carrier heating becomes important for devices from deep-submicron processes. As a result the power supply voltage is almost independent of design rule for the deep-submicron process (V/sub dd/<or=2.5 V).<<ETX>>

Shallow P + -Junction Technology for 0.25 μm CMOS

A preamorphisation technology for fabrication of shallow p⁺-junctions for 0.25 μm CMOS was studied. Silicon and germanium ions were used for preamorphisation. A low energy BF<inf>2</inf>⁺ implantation was used for the formation of the p⁺-region. The physical (SIMS,XTEM) and electrical characterisation of shallow p⁺-junctions will be presented. Large p⁺-diodes and 0.25 μm PMOS transistors were fabricated. The best results were obtained for Ge preamorphised material. Low leakage current p⁺-junctions with depth of 0.15 μm were obtained. However, the preamorphisation technology is complex, has a small process window for shallow p⁺-junctions and the benefits over a conventional approach are not significant. Excellent results were obtained for shallow p⁺ junctions (0.18 μm) fabricated with conventional BF<inf>2</inf>⁺ implants with reduced implantation energy and thermal budget.

Lightly N/sub 2/O nitrided dielectrics grown in a conventional furnace for E/sup 2/PROM and 0.25 /spl mu/m CMOS

For deep-submicron CMOS transistors and FLOTOX E/sup 2/PROM devices a considerable improvement in reliability and performance can be achieved when nitrided dielectrics are used. We developed an N/sup 2/O nitridation technology for a conventional furnace. Oxidation and nitridation are done in one run with a two-step and low-thermal budget processing to grow a dielectric layer with a thickness of 6-10 nm.<<ETX>>

Device Characterisation of a High-Performance 0.25 μm CMOS Technology

The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were obtained. Hot carrier degradation experiments showed that NMOS devices could operate at 2.5 V supply voltage. The delay per stage of a non-optimized 51-stage ringoscillators fabricated in the 0.25 μm process was 62 ps at 2.5 V supply voltage which is a 1.5 times improvement over the delay obtained in a 0.5 μm CMOS technology at 3.3V.