R. Fritschi

Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture

A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOS transistor and a suspended metal membrane in a unique metal-over-gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (<20 nm) is essential for a high C/sub on//C/sub off/ ratio (>100) and a low spring constant (<100 N/m) is needed for low voltage (<5 V) actuation. An adapted fabrication process is reported.

Silicon sacrificial layer dry etching (SSLDE) for free-standing RF MEMS architectures

A novel Silicon Sacrificial Layer Dry Etching (SSLDE) technique using sputtered amorphous or LPCVD polycrystalline silicon as sacrificial layers and a dry fluorine-based (SF/sub 6/) plasma chemistry as releasing process is reported with a detailed experimental study of the release etching step. The process is capable of various applications in surface micromachining process, and can be applied in fabricating RF MEMS switches, tunable capacitors, high-Q suspended inductors and suspended-gate MOSFETs. The developed SSLDE process can release metal suspended beams and membranes with excellent performance in terms of etch rate (up to 15 /spl mu/m/min), Si:SiO/sub 2/ selectivity and is fully compatible with standard MEMS processing equipment and CMOS post-processing.

The suspended-gate MOSFET (SG-MOSFET): a modeling outlook for the design of RF MEMS switches and tunable capacitors

This paper reports on the modeling and key design aspects of an innovative MEMS device: the suspended-gate MOSFET (SG-MOSFET). Based on the coupled-electromechanical equations describing the suspended gate actuation, we present the investigation of the pull-in voltages and of the capacitance switching and tuning ranges for RF applications. A quasi-analytical model is developed for the gate-to-substrate capacitance of the SG-MOSFET and then, validated by numerical simulation. A SPICE macromodel using a polynomial voltage-controlled source is validated for the DC simulation of the SG-MOSFET. Guide lines for the low-voltage design of an SG-MOSFET RF switch are detailed.

A novel RF MEMS technological platform

A novel MEMS technological platform for RF passive components, namely RF MEMS switches, tuneable capacitors and high-Q suspended inductors, is reported. The proposed process employs a metal (Al, AlSi or Cu) as active movable layer and amorphous silicon or polycrystalline silicon as sacrificial layers, providing multi-air-gaps. Various types of substrates like bulk silicon and SOI can be used. Full-dry releasing of suspended beams and membranes is performed with SF/sub 6/ or XeF/sub 2/, with unrivalled yield/reproducibility compared with any other wet etching techniques. The platform is used to validate new MEMS architectures and concepts, such as the suspended-gate MOSFET that can serve as both RF capacitive switches and tuneable RF capacitors.

High Quality Factor Copper Inductors on Wafer-Level Quartz Package for RF MEMS Applications

The paper proposes and validates a new doubly functional quartz wafer-level package concept for MEMS devices. In addition to the mechanical and environment protection, thick-Cu high-Q inductors for RF applications are made within the package processing. A double-side processing of a quartz wafer is reported. While the top side of the quartz is used to realize quartz-embedded horizontal plane Cu inductors, the bottom side is thermo-mechanically bonded on an active wafer using an SU8 photoepoxy semi-hermetic seal. A successful fabrication results in terms of very good adhesion of SU8 bonding, compatibility with fluorine plasma chemistry for MEMS release and very good RF performances (excellent quality factors, higher than 30 at 2 GHz, and self resonant frequency above 6 GHz) was demonstrated

A current density distribution approach to the optimisation of RF-MEMS variable capacitors

An argument for the geometry based frequency range extension of tunable MEMS capacitors is presented. It is shown that, besides reducing the length of the feed arms, the parasitic inductances in a parallel-plate MEMS capacitor can be reduced further by optimising the plate geometry. Extension of the self resonance frequency is demonstrated with reduced circumference of the plate, due to high-frequency currents travelling around the edge of the plate and acting as a major component affecting the self-resonance frequency (SRF) of the capacitor. Full-wave 2.5-D electromagnetic simulation results using Agilent EEsofs ADS Momentum are presented that demonstrate the improvement in self-resonance frequency of circular and symmetrically fed structures. It is shown that efforts in shortening current paths by means of slots did not yield significant further improvement.

Dry Etching Techniques of Amorphous Silicon for Suspended Metal Membrane RF MEMS Capacitors

Reference NANOLAB-CONF-2002-010View record in Web of Science Record created on 2007-10-10, modified on 2017-05-10