R. Gillon

Comparison of TiSi2 , CoSi2, and NiSi for Thin‐Film Silicon‐on‐Insulator Applications

TiSi2, CoSi2, and NiSi self-aligned silicide processes have been studied, compared, and applied to thin-film silicon-on-insulator technology. Compared to TiSi2, CoSi2 and NiSi have the advantages of wider process temperature window, no significant doping retarded reaction, narrow runner degradation, and thin-film degradation. Therefore, they are more suitable for thin-film silicon-on-insulator technology. N-type field effect transistors have been fabricated in a complementary metal oxide-semiconductor compatible thin-film silicon-on-insulator technology with titanium, cobalt, and nickel self-aligned silicide processes for low-voltage, low-power microwave applications. The initial thicknesses of titanium, cobalt, and nickel are 30, 13, and 25 nm, respectively. The gate sheet resistances are 6.2, 4.4, and 2.9 Omega/square, respectively, and the total source/drain series resistances are 700, 290, and 550 Omega mu m, respectively. High-frequency measurement results are also presented.

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.

A low-voltage, low-power microwave SOI MOSFET

Summary form only given. Recently, it has been demonstrated that the use of high-resistivity SOI (SIMOX) substrates (5,000 and 10,000 /spl Omega/.cm) yields MOSFETs which offer interesting microwave performances. Indeed unity-gain frequencies (f/sub T/) of 14 and 23.6 GHz and maximum oscillation frequencies (f/sub max/) of 21 and 32 GHz have been reported for effective gate lengths of 0.36 and 0.25 /spl mu/m, respectively, and using supply voltages ranging from 3 to 5 volts. Such devices can be integrated with planar lines to implement MMIC circuits. These transistors were fabricated using a dedicated MOS process, called MICROX/sup TM/, which uses non-standard CMOS features, such as a metal (gold) gate and air-bridge metallisation. In this work, the high-frequency performances of microwave transistors fabricated using a standard fully-depleted SOI CMOS process are described. These devices are, therefore, compatible with analog and digital circuits fabricated using the same low-cost process.

Determining the reference impedance of on-wafer TLR calibrations on tossy substrates

This paper presents an efficient reference impedance determination method, which is applicable to TLR calibrations performed on a wide variety of substrates, including those consisting of low resistivity material. The method is shown to be valid up to 40 GHz. It is based on the comparison of DC-resistance and scattering-parameter measurements of a resistor, a short and an open.

A 1-GHz operational transconductance amplifier in SOI technology

This work investigates the feasibility of realisation of SOI CMOS Operational Transconductance Amplifiers (OTA) operating up to 1 GHz. In contrast to a previously published microwave wideband amplifier driving low ohmic resistive line termination, OTAs for Switched-Capacitor (SC) applications need a high impedance and capacitive output node. In addition applications such as sigma-delta converters require fast OTAs. In order to reduce the settling time, the transfer function should also include a minimal amount of poles and zeros. Consequently in spite of its low voltage gain, this single-stage OTA could be of interest for high-frequency applications.

Modelling and optimising the SOI MOSFET in view of MMIC applications

A small-signal model based on technological parameters is validated by measurements for thin-film fully-depleted silicon-on-insulator nMOSFETs. The model is used to evaluate the impact of technological improvements and to guide the performance optimisation of the device. It is shown that the SOI nMOSFET can be expected to perform suffciently well so as to be eligible for MMIC applications up to 10 GHz.

Advanced SOI CMOS technology for RF applications

Thin film fully depleted silicon-on-insulator CMOS technology, devices and circuits for RF applications are presented. These submicron MOSFET transistors can achieve a maximum oscillation frequency of 30 GHz for a 1 V power supply. This kind of performance and the advantages of the SOI transistors fit the needs for low-voltage low-power RF applications. To demonstrate the capabilities of this technology we present a single stage OTA with a f/sub T/ of 1.1 GHz and /spl phi//sub M/ of 30/spl deg/, and two CMOS mixers with exceptional linearity results.

Direct extraction method of SOI MOSFET transistors parameters

An extraction method for small-signal model parameters of Silicon-on-Insulator (SOI) MOS transistors is presented. This technique allows to obtain the intrinsic and extrinsic parameter values for a high frequency small-signal model directly from scattering parameter measurements. Only two sets of measured S-parameters are required, one set in the zero-bias condition at relatively high frequency to obtain values of series parasitic elements (R/sub G/, R/sub D/ and R/sub S/) and the other in the frequency band and the bias conditions of interest to determine the parallel elements of the equivalent circuit.

Direct Extraction of the Nonquasi-Static Small-Signal Model of MOSFET's

A new extraction scheme is proposed, which allows to determine all the equivalent circuit elements values from S-parameters measurements at a single bias point in saturation. Exploiting the specific shape of a set of impedance loci, the new procedure uses linear regression techniques to solve the extraction problem. The resulting algorithm is very simple and efficient when compared to optimiser-driven approaches. Taking into account the nonquasi-static (NQS) effects the extracted model allows to characterize the SOI MOSFETs up to 40 GHz.