B. Gentinne

Design of SOI CMOS operational amplifiers for applications up to 300/spl deg/C

Design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300/spl deg/C. The dependence of these parameters on temperature is first described. A new single-stage CMOS opamp model using only these two parameters is presented and compared to measurements of several implementations operating up to 300/spl deg/C for applications such as micropower (below 4 /spl mu/W at 1.2 V supply voltage), high gain (65 dB) or high frequency up to 100 MHz. Trade-offs among such factors as gain, bandwidth, phase margin, signal swing, noise, matching, slew rate and power consumption are described. The extension to other architectures is suggested and the design methodology is valid for bulk as well as SOI CMOS opamps.

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the “gm/ID” methodology is considered further on for quick optimization of the architecture based on the dc open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed.

A physically-based C/sub /spl infin//-continuous fully-depleted SOI MOSFET model for analog applications

An explicit physically-based fully-depleted SOI MOSFET model for all regions of operation is presented. Under quasistatic operation conditions analytical and C/sub /spl infin//-continuous equations are derived for all transistor large and small-signal parameters. Short-channel effects have been included. The calculated characteristics show good agreement with measurements and smooth transitions between regions of operation.

Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C)

Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300 degrees C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFETs are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data.<<ETX>>

Fully depleted SOI-CMOS technology for high temperature IC applications

Thin-film fully depleted complementary metal oxide semiconductor (CMOS) silicon-on-insulator (SOI) technology is currentlly considered as the best mature contender for high-temperature analog or mixed-mode IC applications in the 200-400 degrees C temperature range. This is demonstrated by measurement results of the high-temperature performances of several operational transconductance amplifiers (OTA) with increasing architecture complexity. High-temperature design techniques are also proposed and validated by measurements

Design of thin-film fully-depleted SOI CMOS analog circuits significantly outperforming bulk implementations

Although the reduction of parasitic capacitance and the feasibility of diffusion resistors and capacitors free of junction effects have long been recognized as advantages for the realization of analog circuits on SOI substrates, few SOI analog circuits have been reported mainly because the kink effect severely degrades the output characteristics of thick-film SOI MOSFETs and thereby the performances of analog circuits. Operational amplifier solutions such as the use of body contacts, twin-gate devices or gain-boosting have been proposed but offer little improvement over bulk CMOS counterparts, with the exception of the resistance to elevated temperatures. In the present paper we propose new design models and techniques which, by exploiting the smaller subthreshold swing and body factor of thin-film fully-depleted (FD) SOI MOSFETs, could provide a major breakthrough in order to boost the performances of SOI CMOS analog circuits substantially over bulk implementations, especially in the field of low-voltage low-power applications.

A physically-based C/sub /spl infin//-continuous model for accumulation-mode SOI pMOSFETs

In this paper, we present a unified accumulation-mode (AM) SOI MOSFET model for circuit simulation. The model is valid in all the regimes of normal operation and includes explicit expressions of the drain current and total charges which have an infinite order of continuity; therefore, smooth transitions are assured. Short-channel effects have also been accounted for. We have finally proved that our model accurately fits the transistor characteristics for effective channel lengths down to 0.7-/spl mu/m.

Design and application of SOI CMOS OTAs for high&#8211;temperature environments

Special techniques are presented for the design of SOI CMOS OTAs which have to operate from room up to very high ambient temperatures. The results of several implementations are reported including applications such as in bandgap and current references as well as Σ-Δ modulators with efficient switch design at elevated temperatures.

Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures

Intrinsic gate-capacitance characteristics of long-channel SOI MOSFETs are investigated by measurements up to 300 degrees C and by two-dimensional simulations up to 400 degrees C. Room temperature particularities related to impact ionization and floating body are successfully reproduced by a.c. simulations. Transient simulations are used in order to gain a deep physical insight into the observed phenomena. The contribution of majority carriers generated by impact ionization or back accumulation is clearly established. At high temperature, differences with room temperature behavior observed above and below threshold voltage are explained in terms of thermally generated excess carriers and impact ionization reduction. The analyzed features are the threshold voltage, the subthreshold slope, and particular humps near threshold and subthreshold capacitance values. Implications for analog or digital circuit operation are briefly discussed. Copyright (C) 1996 Elsevier Science Ltd