R.J.G. Goossens

Dual Energy Transport Model with Coupled Lattice and Carrier Temperatures

A Dual Energy Transport (Dual ET) model was developed, that includes Poisson’s equation, carrier continuity equations and the energy balance and thermal diffusion equation. Six variables (electric potential, electron and hole concentrations, electron and hole temperatures, and lattice temperature) can be obtained, describing all electro-thermal effects in the electrons, holes and lattice subsytems. Results for diode breakdown are shown.

A finite element formulation for the hydrodynamic semiconductor device equations

Abstract A new formulation employing the Galerkin/least-squares finite element method is presented for the simulation of the hydrodynamic model of semiconductor devices. Numerical simulations are performed on the coupled Poisson and hydrodynamic equations for one carrier devices. The hydrodynamic equations for a single carrier, i.e. for the electrons or holes, resemble the compressible Navier-Stokes equations with the addition of highly nonlinear source terms and without the viscous terms. The governing equations are nondimensionalized to improve the conditioning on the resulting system of equations and the efficiency of the numerical algorithms. Furthermore, to establish the stability of the discrete solution, the system of hydrodynamic equations is symmetrized by considering generalized entropy functions. A staggered solution strategy is employed to treat the coupled hydrodynamic and Poisson equations. Numerical results are presented for one-dimensional and two-dimensional one-carrier n + - n - n + devices. The presence of velocity overshoot has been observed and it is recognized that the heat flux term plays an important role in the simulation of semiconductor devices employing the hydrodynamic model.

An automatic biasing scheme for tracing arbitrarily shaped I-V curves

A scheme for automated tracing of arbitrarily shaped I-V curves is presented. Tracing out the I-V curves for complicated device phenomena such as breakdown in bipolar transistors and latchup in CMOS structures using conventional device simulation techniques requires a priori knowledge of the shape of the I-V curve and thus is not suitable for exploring new device phenomena. This paper presents a dynamic load-line technique which adapts the boundary conditions as the trace progresses to ensure convergence. By monitoring the slope of the curve, an optimal boundary condition is determined for each point. The boundary condition consists of a voltage source and load resistance corresponding to a load line which is orthogonal to the differential resistance at each point. This orthogonality is defined in a coordinate system scaled by the DC resistance. Step size between points is also defined by this scaling and is varied according to a smoothness criterion. The algorithm guarantees fully automatic tracing of any I-V curve without prior knowledge of the curves characteristics. Its implementation is completely external to the device simulator, i.e., it simply sets up the boundary conditions to be used by the simulator. Curve tracing examples which validate the algorithm are discussed. >

Accurate modeling and numerical techniques in simulation of impact-ionization effects on BJT characteristics

The inclusion of impact ionization in device simulation often suffers from numerical instability. In the present work, a general technique is demonstrated for applying circuit boundary conditions to achieve numerical stability. This technique has been used in the simulation of BV/sub CEO/ of an advanced silicon bipolar device. An I-V curve was obtained showing a new, previously unreported feature, namely, two distinct regions where snap-back occurs. Measurements on fabricated devices confirmed this phenomenon. A detailed physical explanation for the shape of the I-V curves is provided. The dependence on the width and doping of the epi-layer part of the collector is also analyzed.<<ETX>>

An OO-PDE solver for TCAD apps

Technology computer aided design (TCAD) is concerned with modeling the structural and electrical properties of semiconductor devices. The paper discusses the uses of object oriented (OO) methods to design a new base code for all partial differential equation (PDE) based models.