D. Yergeau

Full chip thermal simulation

A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured by the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as the boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data. Both physics and implementation for the thermal simulation are described. The code is applied to the analysis of a realistic design of a CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of the simulation results is presented.

Fast placement-dependent full chip thermal simulation

A general purpose semiconductor device/process simulator, PROPHET, has been adapted for full chip thermal analysis and is capable of quickly (/spl sim/1 minute CPU time) assessing the impact of functional block placement on chip temperature distribution. The key to fast simulation is a new algorithm which maps the heat generation of functional blocks to a coarse mesh while maintaining conservation of heat generating sources. Design of two high-performance CPU chips based on bulk CMOS and SOI technologies, with total power consumption of 100 and 60 watts, respectively, has been evaluated for thermal performance using this approach. Excellent results have been achieved in terms of benchmarked accuracy and computational efficiency. Up to seven interconnect layers have been included in the simulation; effects of packaging are modeled using two capping thermally resistive layers on top and bottom of the chip. Considering the extremely non-uniform nature of interconnect/interleaving-insulating layers, anisotropic thermal conductivity is a critical factor in modeling thermal properties and has been implemented in the simulator. The potential benefit of using pure silicon (Si-28), which has a higher thermal conductivity than that of natural silicon (1.6 times as big at the room temperature), in reducing the peak chip temperature has also been studied. It is shown that with a power consumption level of 100 watts, the peak temperature can be lowered by about 10% (from 136 to 123/spl deg/C).

ALAMODE: A Layered Model Development Environment

To accurately simulate modern semiconductor process steps, TCAD tools must include a variety of physical models and numerical methods. Increasingly complex physical formulations are required to account for effects that were not important in previous generation of technology. As a specific example, the impurity diffusion mechanisms owing to point defects and damage kinetics are not well understood, and thus flexibility in definition of models is highly desirable. An object-oriented approach has been applied to implementing a 1-2-3D finiteelement dial-an-operator PDE solver. The control interface is based on Tcl and allows layered access to model definitions and solution techniques.

Next generation Stanford TCAD-PISCES 2ET and SUPREM 007

Different aspects of Process and Device Simulators developed at Stanford are demonstrated. For PISCES 2ET, a new transport model is benchmarked in comparison to other simplified formulations. Support utilities related to curve tracing are demonstrated. The modular integration of standard tools such SUPREM 4GS and SPEEDIE with a heterogeneous set of other simulators using an agent-based approach (007) is demonstrated.<<ETX>>

Modeling and simulation of phonon boundary scattering in PDE-based device simulators

In this work, the effect of phonon boundary scattering on the heat transfer in thin silicon layers and close to interfaces was investigated. The modeling is applicable to silicon-on-insulator (SOI) devices as well as to conventional bulk technology. From a linearized Boltzmann transport equation (BTE), anisotropic local thermal conductivities are derived. A separate expression is formulated for the case of a bulk device where only one interface is present. Anisotropy was implemented as a finite element-based operator into the PROPHET device simulator and a demonstration of the new electrothermal modeling was made for a conventional MOSFET. The anisotropic local thermal conductivities lead to a temperature increase /spl sim/30% higher at the gate oxide interface compared to conventional modeling.

Quantum transport model for sub-100 nm CMOS devices

Even at room temperature, sub-100 ,nm CMOS devices are strongly affected by quantum mechanical effects. In addition to commonly-known energy quantization in the channel, a charge dipole is observed to appear in the poly-gate, which shifts the threshold voltage in a different way from channel quantization. Moreover, due to the multi-dimensional nature of the structure, conventional Schrodinger/Poissons equation solutions in 1D are no longer adequate for predicting the device characteristics. In this paper, two macroscopic, multi-dimensional quantum transport models, density gradient (DG) and non-equilibrium Greens function (NEGF), are discussed. Validity and application scope are established through comparing to measured data and benchmarking with MIT well-tempered MOSFETs (wtm25 and 90 nm, respectively). It is shown both qualitatively and quantitatively that quantum effects are now required in profile calibration and inverse modeling.

Efficient 3D mesh adaptation in diffusion simulation

Summary form only given. Diffusion simulation is an important part in todays TCAD research. While many works have been done on 2D mesh adaptations in diffusion simulation, 3D mesh adaptation remains a challenging area due to the excessive amount of grid points most mesh generation algorithms produce. In this paper, we apply a generalized octree grid generation algorithm for mesh adaptation. It has the advantage of reducing the number of nodes necessary for accurate simulations. New nodes are added efficiently to reflect the changing position of the junctions and old nodes are removed when they no longer have simulation significance.

A Common Mesh Implementation for Both Static and Moving Boundary Process Simulations

This paper illustrates a common mesh implementation for use in both static and moving boundary process simulations. By using a single mesh server to support the different requirements of those two types of process simulations, it eliminates many interfaces between different simulators and simplifies the simulation process flow. Each simulation module only needs to communicate directly with the mesh program through a well defined common procedure interfaces. By providing a persistent and consistent storage of mesh and field data, the mesh server also greatly reduces the possibility of data loss when transported between simulation steps.

Algorithm for evaluating nodal vector quantities in device simulation and its applications to modeling quantum mechanical effects in sub-50nm MOSFETs

An accurate and general algorithm for evaluating vector quantities, such as electric field, at the nodes in a finite volume discretization is presented. The algorithm is based on the integral form of Poissons and the carrier continuity equations. Application to the analysis of sub-50nm MOSFETs with quantum mechanical (QM) effects is demonstrated. Other applications include the coupled electrothermal simulation (Joule heat) and modeling of impact ionization.

An OO-PDE solver for TCAD apps

Technology computer aided design (TCAD) is concerned with modeling the structural and electrical properties of semiconductor devices. The paper discusses the uses of object oriented (OO) methods to design a new base code for all partial differential equation (PDE) based models.