R.K. Nahar

Diffusivity of Al in Ti and the effect of Si doping for very large scale integrated circuit interconnect metallization

Interaction between Ti/Al and Ti/AlSi layered structures is studied by the resistivity measurements. The change in the resistivity of the structure is correlated to the rate of formation of an intermetallic transition metal compound due to interaction between Al and Ti. It is found that the presence of Si inhibits the interaction. As the reaction rate of the intermetallic compound formation is reduced the activation energy increases. The diffusion coefficient of Al in Ti reduces to a value 6.6×10−17 from 6×10−14 cm2/s and the amount of Ti consumed is reduced by about two orders of magnitude at 450 °C for Ti/AlSi. The results are discussed and implications for multilevel metallization are pointed out.

The yield models and defect density monitors for integrated circuit diagnosis

Abstract In IC manufacturing, the yield of a product is of important consideration. The yield of a circuit is governed by the defects developed in the circuit during fabrication. The accurate identification of the fault and its location helps in improving yield and in reducing development time. This paper reviews the yield models used in predicting the IC yield in semiconductor manufacturing and discusses the practical approach to yield analysis. An approach to systematic process diagnosis by IC structural decomposition is discussed. The design method and layout of some of the defect density test structure monitors are discussed. An example of the process problem analysis is also given.

On the fabrication of thin film MICs from substrate cleaning to pattern delineation

Abstract The processing technology for fabricating thin film MICs is discussed. All the process steps starting from the ceramic substrate cleaning, the substrate metallization with NiCr-Cu-Au sputtered layers, photolithography and the chemical etching are described. The practical problems, important precautions and the optimized processing parameters for the development of reproducible MICs is presented.

Development and performance characterization of the lightly doped drain MOS transistor

Abstract The lightly doped drain transistor is an important technology to reduce hot electron degradation in near and sub-micron devices. The developmental work for establishing an LDD technology is reported. The salient features of this work are: fabrication of a 1-μm gate length LDD MOS transistor, establishment of a new C-V technique for identification of LDD structure and characterization of hot electron generation and degradation. The results are compared for a normal transistor and an LDD transistor with difference schedules. It is shown that the degradation is reduced for a critical range of n− concentration and is a complex function of many process parameters.

On the electrical resistivity and chemical etching of TiSi2 thin films sputtered from a composite target

Abstract The electrical resistivity of TiSi 2 thin films sputtered onto an oxidised Si substrate using a composite alloy target is studied. It is found that the as-deposited films show high resistivity. Annealing the films at an elevated temperature leads to a significant fall in the resistivity. An optimum sheet resistance of 2om tq −1 is obtained after annealing at 800°C for 30 min in argon ambient. The effect of annealing temperature on resistivity is studied. The sheet resistance is also found to be affected by the magnitude of the substrate bias during film deposition. The data are given. The patterning of TiSi 2 thin films by wet chemical etching for device applications is described.

Contact resistance characteristics with AlSi alloy metallization

Abstract Contact resistance characteristics of n + Si shallow junctions metallized by sputtering an AlSi 2% alloy were investigated for different contact window sizes varying from 2 to 8 μm. The increase in the contact resistance with reducing contact area is measured employing Kelvin test structure. The effect of AlSi microstructure, silicon precipitation and annealing cycle on the contact resistance is discussed.

Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Abstract Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.

The effect of scaling on contact and interconnect properties with sputtered TiSi2 metallization

Abstract Investigations are made on contact and interconnect properties for scaling MOS transistor technology employing sputtered TiSi 2 metallization. The contact resistance of different contacts varying in size is measured for n + SiTiSi 2 shallow junction contacts using Kelvin test structures. It is found that the contact resistance almost doubles when the contact size is reduced from 5 to 2 microns. The results are compared with the conventional AlSi 2% contact metallization. The electrical and structural properties of n + poly SiTiSi 2 composite structures are studied as gate and interconnect metallization. The optimum conditions for doping thin poly-Si without affecting thin gate dielectric properties is given. The sheet resistance for the polycide structures is reduced to 2 ohm sq −1 from 40 ohm sq −1 for poly-Si structures for gate metallization. The thermal ability of structures is also examined and the results are discussed.

The filling of via-holes by a sputtered AlSi alloy and the development of a two-level metallisation structure

Abstract Filling via-holes with metal films is one of the most important processes for the development of a multi-level metallisation system. By employing rf bias sputtering, vias of different feature sizes were filled with AlSi films. The process of via-hole filling and the effect of substrate voltage is described. The surface topography and cross section of the filled via-holes are shown. A two-level metal interconnection structure using sputtered AlSi was fabricated. The structure was characterised for the intra-level and inter-level shorts and the continuity of via chains. The process is described and the results are presented.

Improvement in narrow channel effect by an alternative isolation technology

An isolation technique based on simple modification of a conventional isolation technique is presented. It gives improvement in narrow channel effect. The concept is explained and applied to the development of scaled MOS transistors. The performance of field and active area transistors fabricated using the conventional technique is compared with that obtained using the new isolation technique. It is shown that the new isolation technique eliminates load current reduction of depletion transistors and increases the threshold voltage of enhancement transistors with width. Improvement in delay time produced by the proposed isolation technique compared with conventional isolation is evaluated using ring oscillators. It is shown that for near micron and submicron technologies, the delay time would be reduced with the alternative isolation technique.