W.S. Khokle

Window size effect on lateral growth of nickel silicide

Window size effect on lateral growth of nickel silicide in contact windows cut into oxide grown on Si (100) is studied. The growth rate is found to be independent of window size and follows the diffusion‐limited process with activation energy of 1.5 eV. The Si erosions are observed to grow due to predominant Si diffusion for vacuum anneal above 600u2009°C. This phenomenon becomes greatly pronounced with fine windows of 2 μm in diameter. We attribute this to (i) an enhanced stress level in fine windows causing reduction in the growth temperature of epitaxial NiSi2 in the windows and (ii) difference in surface energies of epitaxial NiSi2 formed and the Si substrate resulting in the shrinkage of the epitaxial NiSi2 dimension in the window. No such behavior is observed under identical conditions when Si (111) is used. We believe this is due to the fact that the lateral growth of nickel silicide in this case is about a quarter of that for Ni‐Si (100) lateral samples. Finally the technological importance of this study is pointed out.

Properties of the fluorine-implanted Si-SiO2 system

Abstract Fluorine was impregnated at the Si-SiO2 interface by implanting fluorine ions (19F+) into silicon at low energy (20 keV) to a dose in the range 1011–1015 ions/cm2. Studies were carried out for two cases: first, silicon was oxidised in dry oxygen after 19F+ implantation and second, silicon was implanted with 19F+ after its oxidation to a 207 A thick dry thermal oxide. In both the cases, high frequency capacitance-voltage (HF C-V) measurements show reduction in the midgap interface state density (Nss) nearly by one order of magnitude. Another important observation was that the incorporation of fluorine reduces the oxidation rate of silicon without deteriorating the interface properties.

On the role of fluorine in BF2+ implanted silicon

The role of fluorine atoms on the transformation of surface Si into an amorphous layer after the implantation of molecular BF2 ions has been investigated by the electron spin resonance (EPR) technique. The critical dose of BF2 ions necessary to amorphize the Si at a particular energy is determined experimentally from EPR data analysis. The results reveal that in the ion energy range of 25–150 keV, the critical dose required for BF2 ions was much lower (⩽2.5 × 1015ionscm−2) than compared to the critical dose for B+. The additional damage produced by heavy fluorine atoms, split from BF2 ions, is found responsible for providing the necessary level of amorphization. As an application of BF2+ implantation, shallow p+−n junctions with junction depth and sheet resistivity as low as 0.20 μm and 100 Ω □−1, respectively, were fabricated by two-step annealing.

A new approach for the preparation of in situ superconducting BSCCO films

The paper reports a new approach, based on low-pressure on-axis sputter deposition followed by high-pressure plasma treatment (OPT) for the preparation of in situ superconducting Bi-Sr-Ca-Cu-O (BSCCO) films with a high-Tc phase. It was observed that OPT is essential to lower the room-temperature resistance and to achieve superconduction in the films.

Diffusivity of Al in Ti and the effect of Si doping for very large scale integrated circuit interconnect metallization

Interaction between Ti/Al and Ti/AlSi layered structures is studied by the resistivity measurements. The change in the resistivity of the structure is correlated to the rate of formation of an intermetallic transition metal compound due to interaction between Al and Ti. It is found that the presence of Si inhibits the interaction. As the reaction rate of the intermetallic compound formation is reduced the activation energy increases. The diffusion coefficient of Al in Ti reduces to a value 6.6×10−17 from 6×10−14 cm2/s and the amount of Ti consumed is reduced by about two orders of magnitude at 450u2009°C for Ti/AlSi. The results are discussed and implications for multilevel metallization are pointed out.

An improved self aligned silicide process for VLSI

Abstract An improved self aligned silicide process has been developed for VLSI applications. This process requires no spacer oxide walls. A 6 μm feature size exchange IC was employed as the test vehicle. The titanum disilicide and cobalt disilicide were used as the silicides at the S, D and G levels. These were formed by two step vacuum annealing methods. The excellent results were obtained with both of these silicides. The sheet resistance of TiSi 2 (1 Ω sq. −1 ) was lower than that of CoSi 2 (1.5 Ω sq. −1 ). The SEM has shown no lateral growth with either silicides. Further 0ork is continuing to implement it in the test vehicle with 2–3 μm feature size.

Air bridge and via hole technology for GaAs based microwave devices

This paper describes the process parameter dependence of air bridges and via holes of different dimensions for GaAs based microwave devices and ICs. Process conditions and technologically feasible optimum dimensions of the air bridges for circuit layout are suggested. A wet etching technique for the formation of extremely small (15×15 micron) via holes is also described.

Specific resistivity of a metal-n GaAs OHMIC contact with an intermediate N+ layer

Abstract The specific contact resistivity ρc of a metal-n GaAs structure, over a wide range of carrier concentrations in the intermediate layer (5 × 1018–5 × 1020 cm−3) and in the substrate (1015−1017 cm−3) is calculated. The results which are presented graphically demonstrate the dependence of ρc on metal-semiconductor barrier height from 0.2 eV–0.8 eV. A comparison with the measured data of an alloyed AuGeNi-n GaAs system, suggests that the calculations corresponding to a concentration of 5 × 1018 cm−3 in the layer and barrier height of 0.4 eV give the best fit based on the experimental observations. It is hoped that the results can be used as a guideline in developing ohmic contacts of ultra low resistance values.

Effect of time-dependent development process on the limit of proximity exposure compensation in electron beam lithography

Abstract In our earlier papers, it was pointed out that the limit of proximity exposure compensation (PEC) in electron beam lithography using the dose correction technique is achieved if the dose correction factors are derived from the electron energy dissipation distribution (EED) at a depth in the resist where it has maximum lateral spread. The energy threshold criterion for the development process was used (this implicitly assumes a time-independent development process), to show that under such limiting PEC the resist edge slope of isolated and closely spaced line patterns becomes nearly equal to the edge slope of a single beam line. In this paper we show the effect of a time-dependent development process on the resist edge slope and pattern dimensional accuracy, when PEC is at its limits. The two developers 1:3 MIBK:IPA and MIBK are considered. A two-step development process which combines the advantages of the two developers is shown to provide much better control over the resist edge slope, pattern dimensional accuracy and process flexibility. Finally, the results of different time-dependent development processes are compared with the results when the energy threshold criterion is used for the development process.

Effect of fluorine‐ion implantation on buried nitride silicon‐on‐insulator structures

Effect of fluorine‐ion (19F+) implantation on the buried silicon nitride silicon‐on‐insulator (SOI) structures was investigated. Fluorine was introduced before and after the synthesis of buried Si3N4 layers in silicon by high‐dose nitrogen ion (14N+) implantation. Infrared transmission spectropscopy and glancing angle x‐ray diffraction studies show that 19F+ implantation before SOI synthesis inhibits the growth of larger‐size polycrystalline Si3N4 grains, whereas after the synthesis it removes undesired polycrystalline silicon and helps to obtain larger‐grain‐size α‐polycrystalline silicon nitride in few preferred planes.