R.W. Johnson

The changing automotive environment: high-temperature electronics

The underhood automotive environment is harsh and current trends in the automotive electronics industry will be pushing the temperature envelope for electronic components. The desire to place engine control units on the engine and transmission control units either on or in the transmission will push the ambient temperature above 125/spl deg/C. However, extreme cost pressures, increasing reliability demands (10 year/241 350 km) and the cost of field failures (recalls, liability, customer loyalty) will make the shift to higher temperatures occur incrementally. The coolest spots on engine and in the transmission will be used. These large bodies do provide considerable heat sinking to reduce temperature rise due to power dissipation in the control unit. The majority of near term applications will be at 150/spl deg/C or less and these will be worst case temperatures, not nominal. The transition to X-by-wire technology, replacing mechanical and hydraulic systems with electromechanical systems will require more power electronics. Integration of power transistors and smart power devices into the electromechanical actuator will require power devices to operate at 175/spl deg/C to 200/spl deg/C. Hybrid electric vehicles and fuel cell vehicles will also drive the demand for higher temperature power electronics. In the case of hybrid electric and fuel cell vehicles, the high temperature will be due to power dissipation. The alternates to high-temperature devices are thermal management systems which add weight and cost. Finally, the number of sensors in vehicles is increasing as more electrically controlled systems are added. Many of these sensors must work in high-temperature environments. The harshest applications are exhaust gas sensors and cylinder pressure or combustion sensors. High-temperature electronics use in automotive systems will continue to grow, but it will be gradual as cost and reliability issues are addressed. This work examines the motivation for higher temperature operation, the packaging limitations even at 125/spl deg/C with newer package styles and concludes with a review of challenges at both the semiconductor device and packaging level as temperatures push beyond 125/spl deg/C.

Evaluation of piezoresistive coefficient variation in silicon stress sensors using a four-point bending test fixture

The variation of the piezoresistive coefficients from several rosettes on the same die, the same wafer, and finally at different doping levels across a number of wafers was examined. A thorough error analysis of the method of applying a known uniaxial state of stress using a four-point bending (4PB) fixture was completed. A sensor error analysis demonstrated that it is very difficult to determine accurate values for the sum ( pi /sub 11/+ pi /sub 12/) using the common two-element rosette, particularly in p-type material. However, an empirical equation was found that provides an estimate for this coefficient. The second piezoresistive coefficient pi /sub 44/ can be measured accurately. However, the results presented for pi /sub 44/ differ from those of previous authors by some 33%. Thus, it appears necessary to measure this value for a given wafer lot. >

A hybrid 6H-SiC temperature sensor operational from 25/spl deg/C to 500/spl deg/C

6H-SiC buried-gate n-channel depletion-mode junction field-effect transistors (JFETs) were characterized from 25/spl deg/C to 350/spl deg/C in terms of transconductance (g/sub m/), pinchoff voltage (V/sub P/), output resistance (r/sub o/), input resistance (R/sub in/), drain-to-source current at zero gate-to-source voltage (I/sub DSS/), gate-to-source reverse biased leakage current (I/sub GSS/), off-state drain-to-source current (I/sub DSS(off)/), and noise power spectral density (S/sub V/). The 6H-SiC JFETs were used in a hybrid temperature monitoring circuit (tested from -196/spl deg/C to 500/spl deg/C) fabricated at Auburn University for use in numerous industrial applications. Simulation program with integrated circuit emphasis (SPICE) simulations of the temperature monitoring circuits output voltage corresponded well with measured data as a function of temperature. Linear regression (LR) analysis of measured data revealed a notably sensitive (/spl sim/2.3 mV//spl deg/), and an eminently linear (correlation coefficient =-0.0996...over 25/spl deg/C to 500/spl deg/C range) relationship between the measured output voltage and temperature. Below -50/spl deg/C, the output became nonlinear, presumably from carrier freeze-out effects. To the best of our knowledge, this represents the first successful implementation of SiC active devices into a temperature sensor which demonstrated stable operation up to 500/spl deg/C.

Power Device Packaging Technologies for Extreme Environments

Silicon carbide is a wide-bandgap semiconductor capable of operation at temperatures in excess of 300degC. However, high-temperature packaging to interface with the other elements of the electrical system is required. Die attach, wire bonding, and passivation materials and techniques have been demonstrated for use at 300degC. Transient liquid phase bonding has been developed with Au:Sn/Au, yielding high die shear strength after 2000 h at 400degC. Large diameter (250 mum) gold and platinum wire bonding was evaluated for top side electrical contact. Au wire was reliable after 2000 h at 300degC with Ti/Ti:W/Au pads over passivation on the SiC. However, Au wire on Ti/Pt/Au and Pt wire on both Ti/Tl:W/Au and Ti/Pt/Au exhibited passivation fracture with aging. Polyimide has been demonstrated for 2000 h at 300degC in air as a high-voltage passivation layer.

Off-axis sensor rosettes for measurement of the piezoresistive coefficients of silicon

Experimental calibration results for the piezoresistive coefficients of silicon as a function of temperatures are presented. Measurements have been performed using a test chip incorporating a new off-axis 0-45 degrees -90 degrees rosette design. This rosette requires the application of only uniaxial stress for measurement of the three individual piezoresistive coefficients of silicon: pi /sub 11/, pi /sub 12/, and pi /sub 44/. Of even greater potential import, this rosette yields inherently temperature compensated values of the coefficients pi /sub 44/ and pi /sub D/=( pi /sub 11/- pi /sub 12/). P-type off-axis rosettes have been characterized as a function of temperature, and values for the temperature dependencies of pi /sub 44/ and pi /sub D/ are reported. The coefficients pi /sub 44/ in p-type silicon and pi /sub D/ in n-type silicon are needed for an optimized stress sensor on

Silicon hybrid wafer-scale package technology

A wafer-scale packaging technology is discussed. Pretested IC chips are mounted in holes etched through silicon wafers. Chips are interconnected via the wafer using standard multilevel metallization processes. The packaging technology has the potential to provide the flexibility of hybrid techniques with the reliability and density of monolithic fabrication.

Flexible Electronics: Thin Silicon Die on Flexible Substrates

Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.

Corner bonding of CSPs: processing and reliability

The use of chip-scale packages (CSPs) has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow provide the most common solution to improving mechanical reliability. However, capillary underfill dispense, flow, and cure steps and the associated equipment add cost and complexity to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print but before CSP placement. During reflow, the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement, and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and nonunderfilled CSPs. Finite-element modeling results for the drop test are also included.

Wetting characteristics of Pb-free solder alloys and PWB finishes

For a successful transition to Pb-free manufacturing in electronics assembly, it is critical to understand the behavior of Pb-free solders (in bulk and paste form) and their interaction with the Pb-free printed wiring board (PWB) finishes. This paper presents the results obtained from solder paste spread tests and wetting balance experiments with several Pb-free solder alloys and Pb-free PWB finishes. The solder alloys studied were Sn3.4Ag4.8Bi, Sn4.0Ag0.5Cu, Sn3.5Ag and Sn0.7Cu. Eutectic Sn37Pb was used as a reference. The PWB surface finishes were Sn, NiAu, Ag and OSP. Wetting balance experiments were conducted in air while the spread tests were performed in air and nitrogen to understand the effect of reflow atmosphere on the spreading. Surface analysis techniques such as Nomarski phase contrast microscopy, Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS) were used to characterize the as-received PWB finishes. Sequential electrochemical reduction analysis (SERA) was also performed on the as-received PWB test coupons and on the Sn test coupons after multiple reflow cycles. The effect of multiple reflow cycles on the wetting performance, spreading and the surface composition of the PWB finishes was studied.

Lead-free chip scale packages: assembly and drop test reliability

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.