Jeffrey C. Suhling

Fundamentals of delamination initiation and growth in flip chip assemblies

Underfill encapsulation is used with flip chip die assembled to laminate substrates to distribute and minimize the solder joint strains, thus improving thermal cycling fatigue life. Any delaminations that occur at the underfill/die interface will propagate to the neighboring solder bumps and lead to solder joint fatigue and failure. The onset and propagation of delaminations in flip chip assemblies exposed to thermal cycling are governed by the cyclic stresses and damage occurring at the underfill to die interface. For this reason, underfills are optimized by increasing their adhesion strength, interfacial fracture toughness, and resistance to thermal aging. In this work, we have sought to develop a fundamental understanding of delamination initiation and growth in flip chip assemblies through simultaneous characterization of the stress and delamination states at the die to underfill interface. Mechanical stresses on the device side of the flip chip die have been measured using special (111) silicon stress test chips containing piezoresistive sensor rosettes that are capable of measuring the complete 3D silicon surface stress state in the silicon (including the interfacial shear and normal stresses at the die to underfill interface). By continuous monitoring of the sensor resistances, the die surface stresses were measured during post-assembly thermal cycling environmental testing from -40 to 125 C. With this approach, the stress distributions across the chip, and the stress variations at particular locations at the die to underfill interface have been interrogated for the entire life of the flip chip assembly. In order to correlate the stress changes at the sensor sites with delamination onset and propagation, CSAM evaluation of the test assemblies was performed after every 125 thermal cycles. A total of 75 flip chip assemblies with 3 different underfills have been evaluated. For each assembly, the complete histories of 3D die surface stresses and delamination propagation have been recorded versus the number of thermal cycles. With this approach, we have been able to identify the stress histories that lead to delamination initiation for each underfill encapsulant, and the variation of the stresses that occur before and during delamination propagation. The progressions of stress and delamination have been mapped across the entire surface of the die, and a series of stress/delamination videos have been produced. One of the most important discoveries is that the shear stresses occurring at the corners of flip chip die have been demonstrated to be a suitable proxy for prognostic determination of future delamination initiations and growth.

Measurement of thermally induced die stresses in flip chip on laminate assemblies

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150/spl deg/C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

Decision-Support Models for Thermo-Mechanical Reliability of Leadfree Flip-Chip Electronics in Extreme Environments

Modeling tools and techniques for assessment of component reliability in extreme environments are scarce. Previous studies have focused on development of modeling tools at sub-scale or component level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Application of flip-chip assemblies and underfills in benign office environments and wireless applications is not new, however their reliability in extreme environments is still not very well understood. In the current work, the decision-support models for deployment of flip-chip devices under various harsh thermal environments have been presented. The current work is targeted towards government contractors, OEMs, and 3rd party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. In addition, the mathematical models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing presentlydeployed product designs for minimal risk insertion of new packaging technologies. The models serve as an aid for understanding the sensitivity of component reliability to geometry, package architecture, material properties and board attributes to enable educated selection of appropriate device formats. The perturbation approach presented in this paper enables higher-accuracy model prediction by perturbing known accelerated-test data-sets using models, using factors which quantify the sensitivity of reliability to various design, material, architecture and environmental parameters. The models are based on a combination of statistics and failure mechanics. In addition, parameter interaction effects, which are often ignored in closed form modeling, have been incorporated in the proposed hybrid approach. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Convergence between statistical model sensitivities and failure mechanics based model sensitivities has been demonstrated. Predictions of sensitivities have also been validated against the experimental test data.

Measurement of the temperature dependent constitutive behavior of underfill encapsulants

Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulants for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillary flow snap cure underfill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature, strain rate, specimen dimensions, humidity, thermal cycling exposure, etc. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of true underfill encapsulant layers. In the developed method, 75-125 /spl mu/m (3-5 mil) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. Although several underfills have been examined, this work features results for the mechanical response of a single typical capillary flow snap cure underfill. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates.

Measurements and modeling of the temperature dependent material behavior of underfill encapsulants

Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulanls for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillruy flow snap cure undefiill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature. strain rate, specimen dimensions, humidity, thermal cycling exposure. etc. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of hue underfill encapsulant layers. In the developed method, 75-125 pm (3-5 mil) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. Although several underfills have been examined this work features results for the mechanical response of a single typical capillary flow snap cure underfill. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates. In addition, typical creep data are presented.

Application of stress sensing test chips to area array packaging

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Ultra-High Reliability Flip Chip on Laminate For Harsh Environments

In this work, we report on our efforts to develop ultra-high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. -55 to 150 degC). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and unpressurized space applications

Risk Management Models for Flip-Chip Electronics in Extreme Environments

In this work, risk-management and decision-support models for reliability prediction of flip chip packages in harsh environments have been presented. The models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing product designs for minimal risk insertion of new packaging technologies. In addition, qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. Previous studies have focused on development of modeling tools at sub-scale or component level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Multivariate linear regression and robust principal components regression methods were used for developing these models. The first approach uses the potentially important variables from stepwise regression, and the second approach uses the principal components obtained from the eigen-values and eigen-vectors, for model building. Principal-component models have been included because if their added ability in addressing multi-collinearity. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Statistical models developed in the present work are based on failure data collected from the published literature and extensive accelerated test reliability database in harsh environments, collected by center of advanced vehicle electronics. Sensitivity relations for geometry, materials, and architectures based on statistical models, failure mechanics based closed form models and FEA models have been developed. Convergence of statistical, failure mechanics, and FEA based model sensitivities with experimental data has been demonstrated.© 2006 ASME

Physical aging and evolving mechanical behavior of underfill encapsulants

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, the material behavior changes occurring in flip chip underfill encapsulants (silica filled epoxies) have been characterized for isothermal aging at four different temperatures that are below, near, and above the Tg of the material. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain and creep behaviors of the underfill material at several temperatures, after various durations of environmental exposure. A novel method has been developed to fabricate underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, samples were prepared and isothermal aged for up to 6 months at 80, 100, 125, and 150degC. Stress-strain and creep tests were then performed on both non-aged and aged samples at several different temperatures (25, 50, 75, 100, 125, and 150degC). The changes in mechanical behavior were recorded for the various aging temperatures and durations of isothermal exposure.

Reliability of flip chip assemblies subjected to extreme low temperatures

Electronic assemblies are approximately stress free near their assembly temperature, which is typically above 150 degC when encapsulants and solders are involved. As the assemblies are cooled below room temperature, the temperature difference between ambient and stress free conditions becomes extremely high, and the thermal expansion mismatch induced stresses, strains, and deformations in the assembly can become very large. This phenomenon is exacerbated by the changes in material behavior that occur at extreme low temperatures present in proposed NASA lunar and Mars missions. In particular, encapsulants become much more stiff/brittle losing their typical nonlinear/inelastic stress-strain characteristics and high strains to failure, and the yield stresses for solders become very high. In this work, we evaluated the mechanical performance and reliability of flip chip on laminate assemblies subjected to extreme low temperatures. Stress measurements have been made in the flip chip assemblies during thermal cycling using stress test chips incorporating piezoresistive sensor rosettes. The (111) silicon test chips were 5 times 5 mm in size, with perimeter solder balls on a 200-micron pitch. The obtained stress measurement data correlated well with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solder, underfill encapsulant, and PCB from -180 to +150 C to aid in the numerical simulations