Keith A. Jenkins

100-GHz Transistors from Wafer-Scale Epitaxial Graphene

The maximum switching frequency of these devices exceeds that of silicon transistors with similar gate-electrode dimensions. The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length.

Operation of Graphene Transistors at Gigahertz Frequencies

Top-gated graphene transistors operating at high frequencies (gigahertz) have been fabricated and their characteristics analyzed. The measured intrinsic current gain shows an ideal 1/f frequency dependence, indicating a FET-like behavior for graphene transistors. The cutoff frequency f(T) is found to be proportional to the dc transconductance g(m) of the device, consistent with the relation f(T) = g(m)/(2piC(G)). The peak f(T) increases with a reduced gate length, and f(T) as high as 26 GHz is measured for a graphene transistor with a gate length of 150 nm. The work represents a significant step toward the realization of graphene-based electronics for high-frequency applications.

Wafer-Scale Graphene Integrated Circuit

Components such as inductors were fabricated alongside graphene transistors to create integrated radio-frequency mixers. A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

High-frequency, scaled graphene transistors on diamond-like carbon

Owing to its high carrier mobility and saturation velocity, graphene has attracted enormous attention in recent years. In particular, high-performance graphene transistors for radio-frequency (r.f.) applications are of great interest. Synthesis of large-scale graphene sheets of high quality and at low cost has been demonstrated using chemical vapour deposition (CVD) methods. However, very few studies have been performed on the scaling behaviour of transistors made from CVD graphene for r.f. applications, which hold great potential for commercialization. Here we report the systematic study of top-gated CVD-graphene r.f. transistors with gate lengths scaled down to 40 nm, the shortest gate length demonstrated on graphene r.f. devices. The CVD graphene was grown on copper film and transferred to a wafer of diamond-like carbon. Cut-off frequencies as high as 155 GHz have been obtained for the 40-nm transistors, and the cut-off frequency was found to scale as 1/(gate length). Furthermore, we studied graphene r.f. transistors at cryogenic temperatures. Unlike conventional semiconductor devices where low-temperature performance is hampered by carrier freeze-out effects, the r.f. performance of our graphene devices exhibits little temperature dependence down to 4.3 K, providing a much larger operation window than is available for conventional devices.

When are transmission-line effects important for on-chip interconnections?

Short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Microwave inductors and capacitors in standard multilevel interconnect silicon technology

Spiral inductors and metal-to-metal capacitors for microwave applications, which are integrated on a silicon substrate by using standard 0.8 /spl mu/m BiCMOS technology, are described. Optimization of the inductors has been achieved by tailoring the vertical and lateral dimensions and by shunting several interconnect metal layers together. Lumped element models of inductors and capacitors provide detailed understanding of the important geometry and technological parameters on the device characteristics. The high quality factors of nearly 10 for the inductors are among the best results in silicon, particularly when using standard silicon technology.

Utilization of a Buffered Dielectric to Achieve High Field-Effect Carrier Mobility in Graphene Transistors

We utilize an organic polymer buffer layer between graphene and conventional gate dielectrics in top-gated graphene transistors. Unlike other insulators, this dielectric stack does not significantly degrade carrier mobility, allowing for high field-effect mobilities to be retained in top-gate operation. This is demonstrated in both two-point and four-point analysis and in the high-frequency operation of a graphene transistor. Temperature dependence of the carrier mobility suggests that phonons are the dominant scatterers in these devices.

State-of-the-Art Graphene High-Frequency Electronics

High-performance graphene transistors for radio frequency applications have received much attention and significant progress has been achieved. However, devices based on large-area synthetic graphene, which have direct technological relevance, are still typically outperformed by those based on mechanically exfoliated graphene. Here, we report devices with intrinsic cutoff frequency above 300 GHz, based on both wafer-scale CVD grown graphene and epitaxial graphene on SiC, thus surpassing previous records on any graphene material. We also demonstrate devices with optimized architecture exhibiting voltage and power gains reaching 20 dB and a wafer-scale integrated graphene amplifier circuit with voltage amplification.

RF circuit design aspects of spiral inductors on silicon

In this experiment, the substrate silicon is removed using micromachining techniques, and the remaining thin-film structure is bonded onto a quartz substrate. The micromachined inductor has Q/sub MAX//spl ap/60 at 6 GHz. The lower resistivity and the greater conductor thickness of copper (Cu) compared to the aluminum (Al) process leads to a 3-4/spl times/ increased Q/sub MAX/ over the entire range of feasible inductance values.

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.